High-Performance Indium-Based Oxide Transistors with Multiple Channels Through Nanolaminate Structure Fabricated by Plasma-Enhanced Atomic Layer Deposition

Abstract

An atomic-layer-deposited oxide nanolaminate (NL) structure with 3 dyads where a single dyad consists of a 2-nm-thick confinement layer (CL) (In 0.84 Ga 0.16 O or In 0.75 Zn 0.25 O), and a barrier layer (BL) (Ga 2 O 3 ) was designed to obtain superior electrical performance in thin-film transistors (TFTs). Within the oxide NL structure, multiple-channel formation was demonstrated by a pile-up of free charge carriers near CL/BL heterointerfaces in the form of the so-called quasi-two-dimensional electron gas (q2DEG), which leads to an outstanding carrier mobility (μ FE ) with band-like transport, steep gate swing (SS), and positive threshold voltage (V TH ) behavior. Furthermore, reduced trap densities in oxide NL compared to those of conventional oxide single-layer TFTs ensures excellent stabilities. The optimized device with the In 0.75 Zn 0.25 O/Ga 2 O 3 NL TFT showed remarkable electrical performance: μ FE of 77.1 ± 0.67 cm 2 /(V s), V TH of 0.70 ± 0.25 V, SS of 100 ± 10 mV/dec, and I ON/OFF of 8.9 × 10 9 with a low operation voltage range of ≤2 V and excellent stabilities (ΔV TH of +0.27, −0.55, and +0.04 V for PBTS, NBIS, and CCS, respectively). Based on in-depth analyses, the enhanced electrical performance is attributed to the presence of q2DEG formed at carefully engineered CL/BL heterointerfaces. Technological computer-aided design (TCAD) simulation was performed theoretically to confirm the formation of multiple channels in an oxide NL structure where the formation of a q2DEG was verified in the vicinity of CL/BL heterointerfaces. These results clearly demonstrate that introducing a heterojunction or NL structure concept into this atomic layer deposition (ALD)-derived oxide semiconductor system is a very effective strategy to boost the carrier-transporting properties and improve the photobias stability in the resulting TFTs.

Specific contact resistivity reduction in amorphous IGZO thin-film transistors through a TiN/IGTO heterogeneous interlayer

“…3 ). The detailed procedure to depict the band diagrams can be seen in the previous study 37 . Consequently, the SBH decreases from approximately 0.4 to 0.2 eV by inserting the 3-/8-nm-thick TiN/IGTO IL.…”

Strong Immunity to Drain-Induced Barrier Lowering in ALD-Grown Preferentially Oriented Indium Gallium Oxide Transistors

“…To date, numerous studies have been reported to increase the μ FE in oxide TFTs using various approaches such as Sn-doped InGaZnO (IGZO), − optimization of the cation composition, − crystallization, − heterojunctions, − dual-gate structures, adjusting channel thickness, and postdeposition annealing (PDA) temperature. , Among them, the crystallization via the PDA is one of the simplest and the most effective approaches to improve the μ FE . However, the crystallization of oxide semiconductors with a ZnO component is generally accomplished at a high temperature (>700 °C) due to its corner-sharing crystal configuration different from In 2 O 3 and Ga 2 O 3 with an edge-sharing configuration crystal structure .…”

Double-gate structure enabling remote Coulomb scattering-free transport in atomic-layer-deposited IGO thin-film transistors with HfO2 gate dielectric through insertion of SiO2 interlayer

“…In this context, several approaches have been proposed to ensure high mobility AOS TFTs, such as heterojunction structures using quasi-two-dimensional electron gas (q2DEG) 5 , 11 , crystallization 10 , 12 , hydrogen doping 7 , and multi-gate architecture 14 – 19 . Amongst, adopting the multi-gate architecture, such as double-gate (DG), tri-gate and gate-all-around (GAA), is considered promising due to the outstanding current boosting ability.…”