High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

Chen, Szu-Hung; Liao, Wen‐Shiang; Yang, Hsin-Chia; Wang, Shea–Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haibin; Wang, Mu‐Chun

doi:10.1186/1556-276x-7-431

Cited by 34 publications

(16 citation statements)

References 20 publications

(25 reference statements)

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“…Several reports describe use of multiple anodisation steps, with removal of alumina between each step, as a means of improving the uniformity of the porous structure. 34,35 Following this strategy a three-step anodisation protocol was optimised. Two relatively long anodisations were used to improve the uniformity of the dimpled template, whereas the third anodisation was very brief to ensure formation of a shallow membrane.…”

Section: Preparation Of Paa Membranesmentioning

confidence: 99%

Carbon nanotube diameter control via catalytic Co nanoparticles electrodeposited in porous alumina membranes

Downard

Golovko

2015

RSC Adv.

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Use of porous anodic alumina (PAA) membranes prevents sintering of metal catalyst particles during growth of carbon nanotubes (CNTs) by chemical vapour deposition (CVD). When a metal catalyst fills the base of the pores, the diameters of the resulting CNTs match those of the pores. This approach is generally limited to PAA membranes with pores $50 nm in diameter presumably due to difficulties associated with metal deposition in very narrow pores and with mass transport of gases during CVD. However, PAA membranes offer the opportunity to grow CNTs using catalyst particles with diameters that are significantly smaller than the pores. Here we investigate the electrodeposition of small amounts of Co into the pores of shallow PAA membranes. Using alternating voltage deposition with membranes that have intact, but thinned, barrier layers we demonstrate that CNTs with a diameter of 25 AE 3 nm can be grown from pores with diameters of 60 AE 4 nm.

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Section: Preparation Of Paa Membranesmentioning

confidence: 99%

Carbon nanotube diameter control via catalytic Co nanoparticles electrodeposited in porous alumina membranes

Downard

Golovko

2015

RSC Adv.

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“…As a solution, an increased dielectric material (high-k) is employed to substitute silicon dioxide (SiO 2 ) in which a thicker dielectric layer can be growth on the top of silicon body without having electrical thickness penalties [5]. The high-k dielectric is normally incorporated with metal-gate for solving the compatibility issue between poly-gate and high-k dielectric that might result in lower on-current (I ON ) [6].…”

Section: Introductionmentioning

confidence: 99%

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

2019

IJRTE

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Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (L g ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (L g ) does contributes a significant impact on the drain current (I D ), on-current (I ON ), off-current (I OFF ), I ON /I OFF ratio, subthreshold swing (SS) and transconductance (g m ). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both I ON and g m (max) are measured at 1680 µA/µm and 2.79 mS/µm respectively. Engineering (FKEKK), UTeM. Her research interest includes process and device simulation of nanoscale MOSFETs device, advanced CMOS design, optimization approach (DOE) and process parameter variability. Z. A. F. M. Napiah received the B.Eng. degree in electrical engineering and the M.Eng. degree in Microelectronic from Universiti Teknologi Malaysia (UTM). He received the Ph.D. degree in Microelectronics from Kanawa University, Japan. He is currently a senior lecturer at Faculty of Electronic and Computer Engineering (FKEKK), UTeM. His research interest includes process and device simulation of MOSFET device, advanced CMOS design and CMOS based Photodetector and Photoreceiver.

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“…1 Recent studies on III-V FETs have shown fascinating characteristics from thin-channel planner MOSFETs. 2,3 III-V junctionless FET devices have also been reported for even superior on-/off-state current ratio. 4,5 InGaAs/InAlAs is one of highly attractive III-V materials due to little lattice mismatch 6 and outstanding heterojunction transport property.…”

Section: Introductionmentioning

confidence: 99%

Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1−xGaxAs channel capping layer

Huang

2015

AIP Advances

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In this work, we study characteristics of 14-nm-gate InGaAs-based trigate MOSFET (metal-oxide-semiconductor field effect transistor) devices with a channel capping layer. The impacts of thickness and gallium (Ga) concentration of the channel capping layer on the device characteristic are firstly simulated and optimized by using three-dimensional quantum-mechanically corrected device simulation. Devices with In1−xGaxAs/In0.53Ga0.47As channels have the large driving current owing to small energy band gap and low alloy scattering at the channel surface. By simultaneously considering various physical and switching properties, a 4-nm-thick In0.68Ga0.32As channel capping layer can be adopted for advanced applications. Under the optimized channel parameters, we further examine the effects of channel fin angle and the work-function fluctuation (WKF) resulting from nano-sized metal grains of NiSi gate on the characteristic degradation and variability. To maintain the device characteristics and achieve the minimal variation induced by WKF, the physical findings of this study indicate a critical channel fin angle of 85o is needed for the device with an averaged grain size of NiSi below 4x4 nm2.

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High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

Cited by 34 publications

References 20 publications

Carbon nanotube diameter control via catalytic Co nanoparticles electrodeposited in porous alumina membranes

Carbon nanotube diameter control via catalytic Co nanoparticles electrodeposited in porous alumina membranes

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1−xGaxAs channel capping layer

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