High-Performance Hardware Description Language simulation: Modeling Issues and Recommended Practices

Abstract

Parallel simulation of hardware description languages (HDL) is no longer solely a subject of largely academic interest; it is now a significant opportunity for mainstream hardware and system designers. System requirements and system fabrication densities often exceed uni-processor simulation capability, while shared-memory multiprocessors, high-speed networks and parallel processors (platforms) are widely accessible. However, recognition and practice of suitable HDL modeling practices are critical to efficiently satisfying performance requirements using parallel tool capabilities. This paper develops a set of recommended modeling practices intended to boost parallel HDL simulation effectiveness. These modeling practices are part of an effort by the IEEE Design Automation Standards Committee (DASC) group on High Performance Modeling for Simulation (HPMSIM) to develop a set of recommended practices for discrete-event and continuous-domain modeling in VHDL, VHDL-AMS and Verilog. Since the optimal modeling style is tightly related to the parallel machine architecture employed and the simulation algorithms used, both this paper and the DASC effort key specific modeling recommendations to processor architecture and simulation algorithm classes. Parallel simulators are a technical and commercial reality, thanks in part to the intrinsically parallel nature of HDLs, especially VHDL and VHDL-AMS. Simulation efficiency achieved when using such simulators is heavily dependent on the modeling style used to write the HDL model source. From this paper, readers will gain an understanding of the style designers can use to effectively exploit a range of parallel simulators. Our primary focus is on modeling guidelines boosting performance. The utilization efficiency of processors, memory and network resources is a critical but somewhat secondary concern motivating these guidelines (in the absence of performance gains, efficiency is immaterial).

A Framework for Distributed Simulation of Asynchronous Handshake Circuits

“…are modelled as "Logical Processes" (LPs) which may be executed on different processors [9]. Distributed simulation has emerged as a particularly promising and viable approach to alleviate the simulation bottleneck in VLSI design and over the past ten years has received considerable attention from researchers in mainstream Hardware Description Languages such as VHDL and Verilog [3,15]. Distributed simulation techniques, albeit ad hoc, are progressively finding their place in innovative commercial hardware design environments (e.g.…”