High-performance hardware accelerators for sorting and managing priorities

Performance evaluation for FPGA-based processing of tree-like structures

“…Firstly, we verified the methods [9,10,11] in software (in C/C++) running on HP EliteBook 2730p (Intel Core 2 Duo CPU, 1.87 GHz) tablet PC and PowerPC PPC405 processor embedded to FPGA Virtex4-FX12 (FX12 prototyping board of Nu Horizons). Secondly, the synthesis and implementation of the circuits from specification in VHDL were done in Xilinx ISE 13.4 for FPGAs Spartan3E-1200 (NEXYS-2 prototyping board of Digilent).…”

“…Secondly, the synthesis and implementation of the circuits from specification in VHDL were done in Xilinx ISE 13.4 for FPGAs Spartan3E-1200 (NEXYS-2 prototyping board of Digilent). Methods [9,10,11] for different TLSs have been implemented and tested using the HFSM model. All circuits were entirely implemented in a single FPGA and external resources were not used at all.…”

“…Q<<2 M ). To speed up the processing another way based on representing initial data in form of an N-ary trees [9] can be used which is: a) notably simpler than tree-walk tables from [12]; and b) permits pipelining technique to be realized. This paper presents detailed evaluation of different treebased sorting techniques in terms of performance and memory requirements.…”

“…Let us consider binary trees first [9,10]. Suppose each node of the tree contains three fields: a value (e.g.…”

“…So, we focus here on experiments with indicated above types of HFSMs for PEs that execute operations over TLS. Processing TLS is evaluated using FPGA circuits, which implement algorithms for data sort [9,10,11].…”