High performance dual-MAC DSP architecture

Kolagotla, R.K.; Fridman, J.; Aldrich, B.C.; Hoffman, M.M.; Anderson, William; Allen, Michael S.; Witt, David; Dunton, R.R.; Booth, L.

doi:10.1109/msp.2002.1012349

Cited by 23 publications

(19 citation statements)

References 2 publications

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“…the output pattern is a "don't care". Synchroscalar Tiles are based on the ADI/Intel Blackfin DSP ISA [20], but with control provided by the SIMD con troller instead of in each tile. Additionally, each of the tiles has a read and a write buffer as shown in Figure 2.…”

Section: Data Orchestration Unit (Dou)mentioning

confidence: 99%

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Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

Oliver¹,

Rao²,

Sultana³

et al.

Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.

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Section: Data Orchestration Unit (Dou)mentioning

confidence: 99%

“…The instruction set was re targeted to the Blackfin ISA [20] and communication mech anisms were added.…”

Section: Cycle-accurate Simulationmentioning

confidence: 99%

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

Oliver¹,

Rao²,

Sultana³

et al.

Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.

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“…We first developed a tile based on the Blackfin Digital Signal Processor (DSP) [6], which can be viewed as hav ing a computational width of two. In order to get a power and area estimate for this processor, we modeled the con trol logic of this processor in VHDL and synthesized it us ing the Synopsys Design compiler.…”

Section: Tile Areamentioning

confidence: 99%

Tile size selection for low-power tile-based architectures

Oliver

Rao

Brown

et al. 2006

Proceedings of the 3rd Conference on Computing Frontiers

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In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this inves tigation as a tile granularity study. This is accomplished by distilling the architectural cost of tiles with different compu tational widths into a system metric we call the Granularity Indicator (GI). The GI is then compared against the com munications exposed when algorithms are partitioned across multiple tiles. Through this comparison, the tile granularity that best fits a given set of algorithms can be determined, reducing the system power for that set of algorithms. When the GI analysis is applied to the Synchroscalar tile architec ture [1], we find that Synchroscalar's already low power con sumption can be further reduced by 14% when customized for execution of the 802.11a reciever. In addition, the GI can also be a used to evaluate tile size when considering multiple applications simultaneously, providing a convenient platform for hardware-software co-design.

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“…We use the voltage frequency scaling given by the Newton's alpha law f= k* Our tile is based on the low power 16-bit VLIW DSPs similar to the Intel-ADI MSA-based Blackfin [7] and the SPXK5 from NEC [19]. The minimum core power is assumed to be 0.07mW/MHz similar to [19].…”

Section: Tile Modelmentioning

confidence: 99%

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture

Oliver

Rao

Sultana

et al. 2005

Power-Aware Computer Systems

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Abstract. Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design in tuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based embedded architecture targeted for multi-rate signal processing applica tions.We present a preliminary design of the Synchroscalar architecture and some design space exploration in the context of important signal process ing kernels. In particular, we find that synchronous design and substan tial global interconnect are desirable in the low-frequency, low-power do main. This global interconnect enables parallelization and reduces pro cessor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.

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High performance dual-MAC DSP architecture

Cited by 23 publications

References 2 publications

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

Tile size selection for low-power tile-based architectures

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture

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