High performance code compression architecture for the embedded ARM/THUMB processor

Xu, Xianhong; Clarke, Christopher; Jones, Samuel T.

doi:10.1145/977091.977154

Cited by 16 publications

(14 citation statements)

References 11 publications

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“…RELATED WORK Most code density research addresses the compressibility of instruction code [36], [37], [38], [39], [40], [41], [42], [4], [43], [44], [45]. Usually what is compressed is compiler-generated RISC or VLIW code, with compression ratios typically in the 50-70% range.…”

Section: Density Of Compiler-generated Binariesmentioning

confidence: 99%

Code density concerns for new architectures

Weaver

McKee

2009

2009 IEEE International Conference on Computer Design

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Abstract-Reducing a program's instruction count can improve cache behavior and bandwidth utilization, lower power consumption, and increase overall performance. Nonetheless, code density is an often overlooked feature in studying processor architectures. We hand-optimize an assembly language embedded benchmark for size on 21 different instruction set architectures, finding up to a factor of three difference in code sizes from ISA alone. We find that the architectural features that contribute most heavily to code density are instruction length, number of registers, availability of a zero register, bit-width, hardware divide units, number of instruction operands, and the availability of unaligned loads and stores.We extend our results to investigate operating system, compiler, and system library effects on code density. We find that the executable starting address, executable format, and system call interface all affect program size. While ISA effects are important, the efficiency of the entire system stack must be taken into account when developing a new dense instruction set architecture. I. BENEFITS OF CODE DENSITYDense code yields many benefits. The L1 instruction cache can hold more instructions, which usually results in fewer cache misses [1]. Less bandwidth is required to fetch instructions from memory and disk [2], and less storage is needed to hold program images. With fewer instructions, more data fits in a combined L2 cache. Also, on modern multi-threaded processors, multiple threads share limited L1 cache space, so having fewer instructions can be advantageous. Denser code causes fewer TLB misses, since the code requires fewer virtual memory pages. Modern Intel processors, for instance, can execute compact loops entirely from the instruction buffer, removing the need for L1 I-cache accesses. Finally, the ability to consistently generate denser code can conserve power, since it enables smaller microarchitectural structures and uses less bandwidthObviously, these benefits can come at a cost. For example, a denser ISA might require larger (and thus slower) pipeline decode stages, more complicated compilers, smaller logical register set sizes (due to limitations in the number of bits available in instructions), or even slower and more complex functional units. Compilers tend to optimize for performance, not size (even though the two are inextricably related): obtaining optimal code density often requires hand-tuned assembly language, which represents yet another tradeoff in terms of programmer time and maintainability. The current push for using CISC chips in the embedded market [8] forces a re-evaluation of existing ISAs. II. METHODOLOGYInvestigations of code density often use microbenchmarks (which tend to be short and not representative of actual workloads) or else industry standard benchmarks (which are written in high-level languages and thus are limited by compiler code generation capabilities). As a compromise, we take an actual system utility, but convert it into pure assembly language in order to...

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Section: Density Of Compiler-generated Binariesmentioning

confidence: 99%

Code density concerns for new architectures

Weaver

McKee

2009

2009 IEEE International Conference on Computer Design

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“…Data that generated by embedded systems are commonly kept on a hard disk, but the hard disk of the typical embedded computer system is small (Lekatsas, Dick, Chakradhar, & Yang, 2005;Xu, Clarke, & Jones, 2004). In particular, flight data recorders have small disk drives and generally only write the disk drives and almost never read them; therefore, compression can be beneficial for such systems.…”

Section: Discussionmentioning

confidence: 99%

Smaller Flight Data Recorders

Wiseman¹,

Barkai²

2013

Journal of Aviation Technology and Engineering

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Data captured by flight data recorders are generally stored on the system's embedded hard disk. A common problem is the lack of storage space on the disk. This lack of space for data storage leads to either a constant effort to reduce the space used by data, or to increased costs due to acquisition of additional space, which is not always possible. File compression can solve the problem, but carries with it the potential drawback of the increased overhead required when writing the data to the disk, putting an excessive load on the system and degrading system performance. The author suggests the use of an efficient compressed file system that both compresses data in real time and ensures that there will be minimal impact on the performance of other tasks.

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“…the compressed file will be much less than 1% of the original data; Horowitz et al, 2012). This explains why the compression concern has resurfaced, even though the memory capacity is much larger now (Yang, Dick, Lekatsas, & Chakradhar, 2005;Xu, Clarke, & Jones, 2004).…”

Section: Motivationmentioning

confidence: 99%

Can Flight Data Recorder Memory Be Stored on the Cloud?

Wiseman¹

2016

Journal of Aviation Technology and Engineering

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Flight data recorders (FDRs, or black boxes) generate data that is collected on an embedded memory device. A well-known difficulty with these devices is that the embedded memory device runs out of space. To avoid getting into this problematic situation, the software of the FDR is designed to operate in a watchful mode, constantly working to minimize the use of memory space; otherwise a larger FDR would be needed. However, larger FDRs can be a problem because they have very rigorous requirements; thus, enlargement is costly. Outcomes of this research include the recommendation to send FDR data to a remote cloud storage system, so the data memory device will be unbounded.

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High performance code compression architecture for the embedded ARM/THUMB processor

Cited by 16 publications

References 11 publications

Code density concerns for new architectures

Code density concerns for new architectures

Smaller Flight Data Recorders

Can Flight Data Recorder Memory Be Stored on the Cloud?

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