High-Performance CML approximate full adders for image processing application of laplace transform

Abstract

Purpose The high demand for fast, energy-efficient, compact computational blocks in digital electronics has led the researchers to use approximate computing in applications where inaccuracy of outputs is tolerable. The purpose of this paper is to present two ultra-high-speed current-mode approximate full adders (FA) by using carbon nanotube field-effect transistors. Design/methodology/approach Instead of using threshold detectors, which are common elements in current-mode logic, diodes are used to stabilize voltage. Zener diodes and ultra-low-power diodes are used within the first and second proposed designs, respectively. This innovation eliminates threshold detectors from critical path and makes it shorter. Then, the new adders are employed in the image processing application of Laplace filter, which detects edges in an image. Findings Simulation results demonstrate very high-speed operation for the first and second proposed designs, which are, respectively, 44.7 per cent and 21.6 per cent faster than the next high-speed adder cell. In addition, they make a reasonable compromise between power-delay product (PDP) and other important evaluating factors in the context of approximate computing. They have very few transistors and very low total error distance. In addition, they do not propagate error to higher bit positions by generating output carry correctly. According to the investigations, up to four inexact FA can be used in the Laplace filter computations without a significant image quality loss. The employment of the first and second proposed designs results in 42.4 per cent and 32.2 per cent PDP reduction compared to when no approximate FA are used in an 8-bit ripple adder. Originality/value Two new current-mode inexact FA are presented. They use diodes as voltage regulators to design current-mode approximate full-adders with very short critical path for the first time.

Design of ternary subtractor using multiplexers

“…The 32 nm CNTFET design kit (Stanford University CNFET Model Website, Stanford Univ., Stanford, CA, USA, 2008) is used for the proposed circuit designs in the Windows environment. The HSPICE tool is used for circuit simulations using Stanford University CNTFET model (Deng and Wong, 2007; Deng and Wong, 2007).…”

“…However, none of these devices have been implemented because of practical limitations such as low current drivability, operating in high temperatures and stability issues (Heo et al, 2018). Over the past decades, carbon nanotubes (CNTs) captivated the circuit industry because of their unique shape and extraordinary physical properties (Iijima, 1991;Uoosefian et al, 2020). The use of CNTs as a channel in the transistor is being studied experimentally to acquire a device called carbon nanotube field-effect transistor (CNTFET) in 1998 (Sahoo et al, 2017).…”

One-Class Arabic Signature Verification: A Progressive Fusion of Optimal Features

“…3b. This method uses a (3 × 3) Laplacian filter kernel matrix [38] to extract edge pictures, and the resulting image is known as an edge (x, y) based on Eq. (3):…”

Design and evaluation of ultra‐fast 8‐bit approximate multipliers using novel multicolumn inexact compressors

“…7 Therefore, several parameters of the circuits related to hardware-level approximation, which mainly targets arithmetic units, 8 can be improved by acceptable accuracy degradation. Image and signal processing have been among the fruitful areas for the employment of imprecise arithmetic circuits such as adders [9][10][11][12] and multipliers. [12][13][14][15][16][17][18][19][20][21] A multiplier is an arithmetic unit with a considerable impact on the performance of the entire system.…”