High Performance Asynchronous Design Using Single-Track Full-Buffer Standard Cells

Ferretti, Marcos; Beerel, Peter A.

doi:10.1109/jssc.2006.874308

Cited by 37 publications

(8 citation statements)

References 15 publications

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“…In order to demonstrate the efficiently of the proposed circuit, we evaluate four types of interfaces; CMOS implementation based on the 4-phase dual-rail encoding technique [2], multiple-valued current-mode (MVCM) circuit implementation based on 1-phase dual-rail encoding technique [5], CMOS implementation based on the single-track protocol [3], and the proposed circuit. Table Ⅲ summarizes the performances calculated by HSPICE simulation with a 90nm CMOS process.…”

Section: Discussionmentioning

confidence: 99%

“…Multiple-Valued Single-Track Protocol Figure 1 shows a channel model between modules based on the proposed asynchronous data transfer by handshake protocol without a clock signal. The proposed asynchronous data-transfer protocol is realized based on the single-track protocol [3], [4]. In the single-track protocol, "Data" and "Spacer" are transmitted by sharing the same communication wire.…”

Section: Multiple-valud Single-track Data Transfermentioning

confidence: 99%

“…The proposed asynchronous data-transfer scheme is realized based on the single-track scheme [3], [4], where wires of request and acknowledge signals are shared. In the proposed single-track scheme, as data and control information are represented by using a multi-level signal, single-wire asynchronous data transfer can be realized.…”

mentioning

confidence: 99%

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High-performance asynchronous intra-chip communication link based on a multiple-valued current-mode single-track scheme

Ohtake

Onizawa

Hanyu

2009

2009 IEEE International Symposium on Circuits and Systems

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Figure 1. Channel model in the proposed asynchronous data transfer. Transmitter Receiver Output Input Data Output Input X TM RM (a) Spacer Output Input Output Input X Transmitter Receiver RM TM (b) TM : Transmit Mode , RM : Receive Mode Figure 2. Operation modes: (a)a request mode and (b) an acknowledge mode.Abstract-This paper presents a high-performance asynchronous data-transfer circuit based on a multiple-valued current-mode single-track scheme for on-chip communication.Since one-bit data and control information are represented by using a multi-level signal in the proposed single-track scheme, one-bit data can be transmitted asynchronously using a single wire between modules. The use of current-mode signaling makes the voltage swing on wires reduced, which achieves high-speed data transfer. Moreover, as the number of current sources is reduced by the reduction of wires, it is possible to achieve low power dissipation. Using the proposed circuit, we achieve a throughput of 0.65 Gbps/wires with power consumption of 0.29 mW at 5mm wire length. This presents a 400% increase in throughput, a 57% decrease in power consumption with respect to a conventional asynchronous circuit, using a 90nm CMOS process.

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Section: Discussionmentioning

confidence: 99%

Section: Multiple-valud Single-track Data Transfermentioning

confidence: 99%

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High-performance asynchronous intra-chip communication link based on a multiple-valued current-mode single-track scheme

Ohtake

Onizawa

Hanyu

2009

2009 IEEE International Symposium on Circuits and Systems

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“…Notice that the output and input channels can have different tokens at the same time, highlighting why this template is a full buffer [1] [2]. Notice also that the NMOS transistor stack (N-stack) is designed to be semi-weak-conditioned in that it will not evaluate until all expected input tokens arrive.…”

Section: Stfb Templatementioning

confidence: 99%

“…For example, two prototype standard-cell libraries in TSMC 0.25µm technology for two different asynchronous templates have demonstrated high-performance [1] [2]. One using a Single Track Full Buffer (STFB) library [1] [2] successfully operate over a wide range of temperatures and voltages, with a measured frequency of over 1.2 GHz at a nominal 2.5 Volts [1]. This should be compared to the typical 300 MHz standard-cell synchronous designs achievable in the same process.…”

Section: Introductionmentioning

confidence: 99%

Design of a High-Speed Asynchronous Turbo Decoder

Golani

Dimou

Prakash

et al. 2007

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)

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This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-performance error correction codes used in applications where maximal information transfer is needed over a limitedbandwidth communication link in the presence of data corrupting noise. Specifically we designed an asynchronous high-speed Turbo decoder that can be potentially used for new wireless communications protocols with close to OC-12 throughputs. The design has been implemented using a new static single-track-full-buffer (SSTFB) standard cell library in IBM 0.18µm technology that provides low latency, fast cycle-time, and more robustness to noise than previously studied single-track full-buffer technology (STFB). A high-speed synchronous counterpart using the same high-speed architecture is designed in the same technology for comparison. The results demonstrate that for a variety of network constraints, the asynchronous design provides advantages in throughput per area. Moreover, the asynchronous design can support very low-latency network constraints not achievable with the synchronous alternative.

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