High performance ASIP implementation of PBDI — A new intra-field deinterlacing method

Abstract

We present techniques used to create a high performance application-specific instruction-set processor (ASIP) implementation of the Pattern-Based Directional Interpolation (PBDI) intra-field deinterlacing algorithm. The proposed techniques focus primarily on an efficient utilization of the available memory bandwidth. They include the use of Very Long Instruction Words (VLIW) and an appropriate choice of custom instructions and application-specific registers in order to form a processing pipeline. We report a speedup factor of 1351 in comparison with a software-only implementation of the algorithm running on a general-purpose 32-bit RISC processor.

Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors

“…We previously reported on a high performance ASIP implementation of the PBDI intra-field deinterlacing algorithm [21]. In this paper, we extend the scope of this work by proposing a systematic ASIP design approach for real-time local neighborhood video processing applications.…”

“…Three intra-field deinterlacing algorithms were implemented, as well as 2-D convolution with four different kernel sizes. Performance results for one of the deinterlacing algorithms were previously published in [21]. All implementations are based on the Xtensa LX2 configurable and extensible processor [29], [30].…”

“…This means that the window slides by two pixels each execution cycle. This can be expressed as (19) Thus (20) and, in the same way (21) This leads to the elimination of two load operations. If the window were wider, it would also be possible to eliminate the additional load operations in this way, and longer shift registers would be formed.…”

“…The architectures of the three implementations are very similar. The architecture of the PBDI implementation is described in detail in [21].…”

“…This exceeds the requirements to process high-definition video in real-time. For example, it is four times the processing speed required to process 1080i high-definition video in real-time at the standard rate of 60 fields per second [21]. However, these numbers do not take into account the latency involved in fetching the input pixels and storing the results offchip.…”