High-performance architectures for elementary function generation

Jun, Cao; Wei, B.W.Y.; Cheng, Jie

doi:10.1109/arith.2001.930113

Cited by 37 publications

(70 citation statements)

References 5 publications

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“…where d i ∈ {0, 1}, n int is the number of bits for the integer part, and n f rac is the number of bits for the fractional part of r. The representation in (1) is two's complement, and so (2), where n f rac is finite, that is exactly √ 2.…”

Section: Preliminaries Definitionmentioning

confidence: 99%

“…For piecewise polynomial approximations, in many cases, the domain is partitioned into uniform segments [2]- [4], [21], [22]. Such methods are simple and fast, but for some kinds of numerical functions, too many segments are required, resulting in large memory.…”

Section: Piecewise Quadratic Approximationmentioning

confidence: 99%

“…We represent c 2i and c 1i as c 2i × 2 −l 2i × 2 l 2i and c 1i × 2 −l 1i × 2 l 1i , respectively. And, we compute the products c 2i (x − q i ) 2 and c 1i (x − q i ) using multipliers for the right-shifted multiplicand, c 2i ×2 −l 2i (x−q i ) 2 and c 1i ×2 −l 1i (x− q i ), and left shifters to restore the products. Applying right shifts reduces the number of bits for c 2i × 2 −l 2i and c 1i × 2 −l 1i (i.e.…”

Section: Reduction Of the Size Of The Multipliermentioning

confidence: 99%

“…However, it requires O(2 n ) search, and is time-consuming. Therefore, we compute the maximum value p by specifying the bits of x from the MSB to the LSB such that 2 …”

mentioning

confidence: 99%

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Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method

Nagayama¹,

Sasao²,

Butler³

2006

IEICE Transactions on Fundamentals of Electronics, Communicatio

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SUMMARYThis paper presents an architecture and a synthesis method for compact numerical function generators (NFGs) for trigonometric, logarithmic, square root, reciprocal, and combinations of these functions. Our NFG partitions a given domain of the function into non-uniform segments using an LUT cascade, and approximates the given function by a quadratic polynomial for each segment. Thus, we can implement fast and compact NFGs for a wide range of functions. Experimental results show that: 1) our NFGs require, on average, only 4% of the memory needed by NFGs based on the linear approximation with non-uniform segmentation; 2) our NFG for 2 x − 1 requires only 22% of the memory needed by the NFG based on a 5th-order approximation with uniform segmentation; and 3) our NFGs achieve about 70% of the throughput of the existing table-based NFGs using only a few percent of the memory. Thus, our NFGs can be implemented with more compact FPGAs than needed for the existing NFGs. Our automatic synthesis system generates such compact NFGs quickly.

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Section: Preliminaries Definitionmentioning

confidence: 99%

Section: Piecewise Quadratic Approximationmentioning

confidence: 99%

Section: Reduction Of the Size Of The Multipliermentioning

confidence: 99%

“…However, it requires O(2 n ) search, and is time-consuming. Therefore, we compute the maximum value p by specifying the bits of x from the MSB to the LSB such that 2 …”

mentioning

confidence: 99%

See 2 more Smart Citations

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method

Nagayama¹,

Sasao²,

Butler³

2006

IEICE Transactions on Fundamentals of Electronics, Communicatio

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“…As transistor densities continue to increase, more of these functions are implemented in hardware. Piecewise-polynomial function approximation, using coefficients stored in a lookup table, is an efficient technique with many papers written on the subject [2][3][4][5][6][7][8][9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Linear and Quadratic Interpolators Using Truncated-Matrix Multipliers and Squarers

Walters

2015

Computers

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This paper presents a technique for designing linear and quadratic interpolators for function approximation using truncated multipliers and squarers. Initial coefficient values are found using a Chebyshev-series approximation and then adjusted through exhaustive simulation to minimize the maximum absolute error of the interpolator output. This technique is suitable for any function and any precision up to 24 bits (IEEE single precision). Designs for linear and quadratic interpolators that implement the 1/x, 1/ √ x, log 2 (1 + 2 x ), log 2 (x) and 2 x functions are presented and analyzed as examples. Results show that a proposed 24-bit interpolator computing 1/x with a design specification of ±1 unit in the last place of the product (ulp) error uses 16.4% less area and 15.3% less power than a comparable standard interpolator with the same error specification. Sixteen-bit linear interpolators for other functions are shown to use up to 17.3% less area and 12.1% less power, and 16-bit quadratic interpolators are shown to use up to 25.8% less area and 24.7% less power.

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