High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

Abstract

technology. To achieve aggressively-scaled active, poly, conWe present an aggressively-scaled high-performance and tact, and metal pitches and thus to create 2x pattern density, low-power bulk CMOS platform technology aiming at large-scale high-NA 193-nm immersion lithography was used to expose the (multi-core) high-end use with 45-nm ground rule. By utilizing a critical layers. The FEOL process flow in which MST is the booster high-epsilon offset spacer and FET specific multiple-stressors for improving the performance ofboth N-and PFET is shown in with highly enhanced strain, world competitive high performance Fig. 2. Also, note that this technology is based on the Y-shaped NFET and PFET drive currents of 1.22/0.765 mA/tm at 100 nA/ eSiGe [1] and millisecond annealing (MSA) [2] integration scheme. tm off-current, and 0.97/0.63 mA/tm at 10 nA/gm off-current at The key features of this flow are the implementation of a highVdl = 1V, respectively, were obtained with minimizing layout de-epsilon offset spacer (HEOS) as the extension offset [3] and mulpendence. This technology also offers a functional high density tiple poly-gate stressors (PGSs) or the stress memorization tech-SRAM with a much smaller cell, i.e., 0.255 giM2. In addition, full-nique (SMT) [4]. Implementing the HEOS leads to better perforporous low-k (k = 2.25) BEOL integration lowers RC delay and mance of both the N-and the PFET, whereas the implementing reduces total circuit delay by 25% at the long wiring region com-the PGSs improves the NFET. Fig. 3 shows TEM cross-sections pared to that of our previous technology.of full-processed core FETs with 32-nm gate lengths with welloptimized unit processes. The impact of the HEOS technique on Introduction linear characteristics is shown in Fig. 4. By enhancing the fringThe rapid growth of the market for mobile computers and ing field with high-epsilon spacer material, the parasitic resisdigital consumer electronics, as well as large-scale computer sys-tance of source-drain extension (SDE) under the spacer is signifitems has led to continuing demands for enhanced performance, cantly decreased, and this results in 7 and 10% increases in linear while maintaining low power consumption. This presents us with currents ofN-and PFETs, respectively. A concern in implementthe great challenge of developing the next generation of technol-ing HEOS is the increase of fringe capacitance, which directly ogy nodes. The possibilities offered by gate oxynitride thick-degrades AC performance. The overlap capacitance, Cov, with ness scaling rather than implementing high-k dielectrics are al-and without using HEOS technology is shown in Fig. 5. Ofcourse, ready at their physical limit, and most ofthe potential for improv-high permittivity of offset spacer increases Cov, in which fringe ing performance, as well as for reducing power consumption de-capacitance is also included; however, the effect of improving pends on the multiple-stressor technology (MST) in high perfor-the drive current is much larger and consequently, total ci...

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