High Performance and Low Leakage 3DSOI Fin-FET SRAM

Abstract

Abstract:In recent semiconductor designs, the major key factors: Competent device simulations, precise device characterization, well power optimization, new architectural design and cost-effective fabrication drives the designers attention towards multi gate transistors as an alternative to MOSFET. Non planner device structures are a competitive edge over planner devices. Silicon-on-Insulator (SOI) FinFETs are hopeful among variety of multi-gate structures as they have simple fabrication, Superior gate control, lower subthreshold leakage and minimized susceptibility to process variations. Low leakage memory cells play a significant role of power consumption in the recent VLSI Systems. In this study, Ultra-low Voltage Asymmetric Short Gate (UVASG) FinFET is modeled with TCAD tools for low leakages and FinFET based SRAM has been proposed as a substitute for the bulk devices.

Soft-Error Reduction and Enhancement of Write Stability and Hold Power Optimization by using 12T SRAM for Aerospace Applications

“…The literature survey in Ch Santhi Rani, D Sudha, Sreenivasa Rao Ijjada [3] comparing the proposed 10T SRAM cell design in both CMOS and Fin FET technologies with existing cell designs in the literature to showcase its advantages in terms of stability and power consumption.Wing-Hung Ki and Chi-Ying Tsui [1] SARP12T is immune to SEUs of both polarities induced at any sensitive node and can recover from SEMNUs that occur at its storage node-pair also consumes the lowest hold power dominance among all the cells under consideration. Ch Santhi Rani, D Sudha, Sreenivasa Rao [2] summarizes the importance of semiconductor memories, the challenges in bulk CMOS scaling, and the advantages of using Fin FET technology as an alternative. Ji Sang Oh and Juhyun Park [7] discusses the challenges faced by conventional SRAM bitcells in the near-V region with a bit-interleaved structure and the proposed solutions to address these challenges, including the differential 7T SRAM bit cell with an additional PMR NMOS transistor.Jae-Won Nam, Ju-Hyeok Ahn [6] discusses the need for advanced security systems for IoT devices, introduces PUFs as a solution, explains different types of PUFs, and highlights the advantages of memory-based PUFs.…”

SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects

“…Double gate FINFETs overcomes scaling hurdles and its significant feature of Fin FETs is that the front and back gates can be made independent and biased to manage the current and threshold voltage. Typical Fin-FET design is presented in the papers [5][6][7].…”