High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM

Seo, Yeongkyo; Kwon, Kon-Woo; Fong, Xuanyao; Roy, Kaushik

doi:10.1109/jetcas.2016.2547701

Cited by 38 publications

(17 citation statements)

References 43 publications

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“…The goal of this work is to improve the cache access latency by designing a standalone memory that can be used in multi-core systems as a shared pipeline cache. For the pipeline processors usually dual port is used to avoid stalling during simultaneous access to the memory [21,22]. The proposed design is based on dual port CAM (DPCAM), which provides simultaneous write and search operations within the CAM memory, if more than one core try to access the memory.…”

Section: Related Workmentioning

confidence: 99%

Dual-Port Content Addressable Memory for Cache Memory Applications

Abumwais¹,

Amirjanov²,

Uyar³

et al. 2022

Computers, Materials &Amp; Continua

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Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM. However, an estimation of the power dissipation showed that DPCAM consumes about 7% greater than a set-associative cache memory of the same size. These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.

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Section: Related Workmentioning

confidence: 99%

Dual-Port Content Addressable Memory for Cache Memory Applications

Abumwais¹,

Amirjanov²,

Uyar³

et al. 2022

Computers, Materials &Amp; Continua

View full text Add to dashboard Cite

show abstract

“…For instance, 2 MB capacity of conventional SOT-MRAM consumes similar silicon area to an 8 MB capacity of MBC-DD SOT-MRAM. Higher memory capacity results in higher performance metrics, such as instruction per cycle (IPC) and energy efficiency due to reduced access counts for the off-chip memory [30].…”

Section: System-level Evaluationmentioning

confidence: 99%

Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory

Ali¹

2020

Integrated Circuits/Microchips

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Spin-orbit torque magnetic random-access memory (SOT-MRAM) has shown promising potential to realize reliable, high-speed and energy-efficient on-chip memory. However, conventional SOT-MRAM requires two access transistors per cell. This limits the use of conventional SOT-MRAM in high-density memories. Thus, various architectures in the literature have been proposed to improve the area efficiency of the SOT-MRAM. In this chapter, these proposals are divided into two categories: non-diode-based SOT-MRAM and diode-based SOT-MRAM cells. The non-diode-based proposals may result in a 1-bit effective area saving up to 50% compared to the conventional SOT-MRAM, whereas the diode-based designs may result in 1-bit effective area-saving of up to 75%. However, the area saving may be accompanied by higher energy and reliability issue penalties. Therefore, here, the various proposals in the literature are presented, highlighting the pros and cons of each design. Moreover, the technology requirements to realize these proposals are discussed. Finally, the various designs are evaluated from both cell and system level perspectives.

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“…Despite using an additional transistor, the bit cell of SOT-MRAM only induces slightly area overhead since the required write current is much lower than that of in STT-MTJ. In addition, the read and write paths are separated in the SOT-MTJ, which is suitable for developing the multi-port MRAM [28], [29]. Based on the transient analyses shown in Fig.…”

Section: Sot-mrammentioning

confidence: 99%

Multi-Port 1R1W Transpose Magnetic Random Access Memory by Hierarchical Bit-Line Switching

et al. 2019

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Emerging Magnetic Random-Access Memory (MRAM) has shown a great potential to replace Static-RAM (SRAM) and Dynamic-RAM (DRAM) in the working memories including Cache and main memory. MRAM benefits from its high-density, fast speed, low standby power, and non-volatility, which provides the possibility to accelerate the computation. In this paper, we present a transpose MRAM (T-MRAM) based on the current MRAM family (Spin-Transfer Torque or STT, Spin-Orbit Torque or SOT,-MRAM) to support read/write operations both in vertical and horizontal dimensions. More importantly, a multi-port 1-Read-1-Write (1R1W) scheme is developed for the proposed T-SOT-MRAM. Thanks to the ultra-fast speed and high power-efficiency, the proposed T-SOT-MRAM can be used to accelerate the computation of Convolution Neural Networks (CNNs) and video coding. The functional validation is performed under a hybrid CMOS/MRAM simulation. According to the evaluation results, the proposed T-SOT-MRAM obtains 1.8× speedup and 28% energy saving of 1R1W operations, compared to the baseline. In addition, T-MRAMs consume less leakage power consumption than the other counterparts. Furthermore, the smaller cell area of the proposed T-MRAMs allows increasing the capacity in order to improve performance efficiency.

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High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM

Cited by 38 publications

References 43 publications

Dual-Port Content Addressable Memory for Cache Memory Applications

Dual-Port Content Addressable Memory for Cache Memory Applications

Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory

Multi-Port 1R1W Transpose Magnetic Random Access Memory by Hierarchical Bit-Line Switching

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