High-Performance and Energy-Efficient Network-on-Chip Architectures for Graph Analytics

Duraisamy, Karthi; Lu, Hao; Pande, Partha Pratim; Kalyanaraman, Ananth

doi:10.1145/2961027

Cited by 17 publications

(8 citation statements)

References 37 publications

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“…17,18 Most of the times, energy-efficient NoC designs have been led to increasing control complexity and latency. [35][36][37][38][39][40][41][42][43][44] Numerous adaptive routing algorithms have been proposed to minimize congestion and to balance network load and hence, to decrease latency in intermediate routers. [45][46][47] For instance, to achieve high reliability and traffic balancing, PDA-FTR, as a fault tolerant routing algorithm that is aware of path-diversity is presented in Reference 47.…”

Section: Related Workmentioning

confidence: 99%

“…On the other side, it is not practical to design a NoC without buffers because removing buffers causes many dead‐locks. Therefore, the optimal approach is using hybrid buffer/bufferless ports with bypass paths in order to provide efficient NoC architectures 35‐43 …”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the optimal approach is using hybrid buffer/bufferless ports with bypass paths in order to provide efficient NoC architectures. [35][36][37][38][39][40][41][42][43] In this article, we propose HiFMP, a high-performance FPGA-based NoC router that provides low latency, low power consumption, and moderate low area. The structure of HiFMP is simple, fine-grain, modular with low hardware usage and it employs several techniques for using the benefits of FPGA devices and for effectively reducing power consumption.…”

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confidence: 99%

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A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Alaei

Yazdanpanah

2020

Concurrency and Computation

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High performance system-on-chip (SoCs) designs have led to high-density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network-on-chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high-performance FPGA-based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low-power NoC router with high performance in terms of energy-efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA-based NoC with mesh topology. Performance evaluations include network-level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures. K E Y W O R D S FPGA, low-power design, multicrossbar, network-on-chip, priority-based router 1 INTRODUCTION In high-density emerging SoC architectures, there are a large number of processing elements (PEs) communicating through intensive on-chip interconnections that significantly affect different aspects of the performance. For large SoCs, point-to-point and bus-based interconnections do not provide efficient on-chip network infrastructures because of large amount of hardware, high latency, high power consumption, and/or complicated synchronization. NoCs, as high-performance architectures, arise to overcome the limitations of traditional on-chip structures. 1-5 NoCs provide high-performance and power scalable and modular interconnections. In addition, with NoC architectures, the system complexity is reduced by separating communication and computation units. A NoC includes routers, links, and network interfaces in order to prepare a network infrastructure for interconnecting PEs. Links of NoCs consist of physical channels (i.e., a group of wires), and optional virtual channels (VCs) as a set of additional buffers in routers. 4-7 The channel bit-width (the number of wires in a unidirectional channel) depends on the bandwidth requirements of the applications and available chip area. Generally, links of NoC have two physical unidirectional channels for fully duplexed communication, allowing data to flow both ways without collisions. 1 Routers are the most important modules of the communication backbone of NoC architectures. So, it is essential to design them with low latency, low power consumption, and high throughput. The router complexity and performance impacts the latency, power consumption, area, throughput, and the cost of on-chip networks. 8 Field programmable gate arrays (FPGAs) are flexible, easy-to-use, and cost effective reprogrammable devices with fast and simple design flow. FPGA designers generally do not need to care for clock distribut...

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Alaei

Yazdanpanah

2020

Concurrency and Computation

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“…We described WiSync [3] in Section 2. Duraisamy et al [27] accelerate graph analytics using an NoC augmented with wireless links to better support irregular communication patterns. In their case, the application is oblivious of the underlying architecture, and the routing mechanism of each node decides whether to use the wireless links or the regular wire lines, based on the destination address.…”

Section: Related Workmentioning

confidence: 99%

“…Recently, on-chip wireless communication has emerged as a promising alternative that supports fine-grained data sharing with low-latency, and is broadcast-friendly [3,23,26,27]. In this environment, broadcasting a short message of 80 bits takes about 4 ns, which is about two orders of magnitude lower than in conventional on-chip networks.…”

Section: Introductionmentioning

confidence: 99%

Replica

Fernando

Franques

Abadal

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

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Data access patterns that involve fine-grained sharing, multicasts, or reductions have proved to be hard to scale in sharedmemory platforms. Recently, wireless on-chip communication has been proposed as a solution to this problem, but a previous architecture has used it only to speed-up synchronization. An intriguing question is whether wireless communication can be widely effective for ordinary shared data. This paper presents Replica, a manycore that uses wireless communication for communication-intensive ordinary data. To deliver high performance, Replica supports an adaptive wireless protocol and selective message dropping. We describe the computational patterns that leverage wireless communication, programming techniques to restructure applications, and tools that help with automation. Our results show that wireless communication is effective for ordinary data. For 64 cores, Replica obtains a mean speed-up of 1.76x over a conventional machine. The mean speed-up reaches 1.89x if approximate-computing transformations are enabled. The average energy consumption is substantially reduced by 34% (or 38% with approximate transformations), and the area increases only modestly.

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