High Performance Accelerator for CNN Applications

Kyriakos, Angelos; Kitsakis, Vasileios; Louropoulos, Alexandros; Papatheofanous, Elissaios Alexios; Patronas, Ioannis; Reisis, D.

doi:10.1109/patmos.2019.8862166

Cited by 16 publications

(8 citation statements)

References 7 publications

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“…On the other hand, studies on CNN hardware acceleration architecture designs are increasing vigorously [29,[35][36][37]. Parallel processing engine (PE) and pipelined architecture are widely used in CNN accelerators to improve bandwidth and reduce latency.…”

Section: Hardware Acceleration For Cnnsmentioning

confidence: 99%

“…However, the PE array is not fully utilized during acceleration because of an inappropriate 12 × 14 array size. Kyriakos et al [36] used a highly pipelined structure in their architecture with each computation operation as a stage. This structure reduces the access to off-chip DRAM, thereby achieving low latency and low power consumption.…”

Section: Hardware Acceleration For Cnnsmentioning

confidence: 99%

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Automatic Deployment of Convolutional Neural Networks on FPGA for Spaceborne Remote Sensing Application

Yan

Zhang

et al. 2022

Remote Sensing

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In recent years, convolutional neural network (CNN)-based algorithms have been widely used in remote sensing image processing and show tremendous performance in a variety of application fields. However, large amounts of data and intensive computations make the deployment of CNN-based algorithms a challenging problem, especially for the spaceborne scenario where resources and power consumption are limited. To tackle this problem, this paper proposes an automatic CNN deployment solution on resource-limited field-programmable gate arrays (FPGAs) for spaceborne remote sensing applications. Firstly, a series of hardware-oriented optimization methods are proposed to reduce the complexity of the CNNs. Secondly, a hardware accelerator is designed. In this accelerator, a reconfigurable processing engine array with efficient convolutional computation architecture is used to accelerate CNN-based algorithms. Thirdly, to bridge the optimized CNNs and hardware accelerator, a compilation toolchain is introduced into the deployment solution. Through the automatic conversion from CNN models to hardware instructions, various networks can be deployed on hardware in real-time. Finally, we deployed an improved VGG16 network and an improved YOLOv2 network on Xilinx AC701 to evaluate the effectiveness of the proposed deployment solution. The experiments show that with only 3.407 W power consumption and 94 DSP consumption, our solution achieves 23.06 giga operations per second (GOPS) throughput in the improved VGG16 and 22.17 GOPS throughput in the improved YOLOv2. Compared to the related works, the DSP efficiency of our solution is improved by 1.3–2.7×.

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Section: Hardware Acceleration For Cnnsmentioning

confidence: 99%

Section: Hardware Acceleration For Cnnsmentioning

confidence: 99%

Automatic Deployment of Convolutional Neural Networks on FPGA for Spaceborne Remote Sensing Application

Yan

Zhang

et al. 2022

Remote Sensing

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“…As a case in point, in some studies such as [38,46], the accuracy was improved to a large extent in AV use cases; however, the detection was not in real-time. In [23,26,51], the PGA accelerator was used to improve the speed which is a costly solution. Besides, in [26], the improvement in execution speed (by 11.5%) was compared against the execution on CPU which is usually the slowest hardware to execute CNNs.…”

Section: Convolutional Neural Network Improvementsmentioning

confidence: 99%

A dynamic discarding technique to increase speed and preserve accuracy for YOLOv3

Martinez‐Alpiste

Golkarnarenji

Wang

et al. 2021

Neural Comput & Applic

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This paper proposes an acceleration technique to minimise the unnecessary operations on a state-of-the-art machine learning model and thus to improve the processing speed while maintaining the accuracy. After the study of the main bottlenecks that negatively affect the performance of convolutional neural networks, this paper designs and implements a discarding technique for YOLOv3-based algorithms to increase the speed and maintain accuracy. After applying the discarding technique, YOLOv3 can achieve a 22% of improvement in terms of speed. Moreover, the results of this new discarding technique were tested on Tiny-YOLOv3 with three output layers on an autonomous vehicle for pedestrian detection and it achieved an improvement of 48.7% in speed. The dynamic discarding technique just needs one training process to create the model and thus execute the approach, which preserves accuracy. The improved detector based on the discarding technique is able to readily alert the operator of the autonomous vehicle to take the emergency brake of the vehicle in order to avoid collision and consequently save lives.

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“…FPGAs can over-come these limitations due to their custom parallel processing capabilities and flexibility. Various CNN implementations on FPGA have been reported in literature [11]- [13], focusing on different aspects, e.g., the optimization of only the convolutional layers [14], [15] or the overall accelerator throughput [16]. There are also SW/HW co-design solutions that exploit the aggregate power of both an embedded processor and the programmable logic [17], [18].…”

Section: Background and Literature Reviewmentioning

confidence: 99%

Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration

Irmak

Ziener

Alachiotis

2021

2021 31st International Conference on Field-Programmable Logic and Applications (FPL)

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Convolutional Neural Networks (CNN) are widely used for image classification and have achieved significantly accurate performance in the last decade. However, they require computationally intensive operations for embedded applications. In recent years, FPGA-based CNN accelerators have been proposed to improve energy efficiency and throughput. While dynamic partial reconfiguration (DPR) is increasingly used in CNN accelerators, the performance of dynamically reconfigurable accelerators is usually lower than the performance of pure static FPGA designs. This work presents a dynamically reconfigurable CNN accelerator architecture that does not sacrifice throughput performance or classification accuracy. The proposed accelerator is composed of reconfigurable macroblocks and dynamically utilizes the device resources according to model parameters. Moreover, we devise a novel approach, to the best of our knowledge, to hide the computations of the pooling layers inside the convolutional layers, thereby further improving throughput. Using the proposed architecture and DPR, different CNN architectures can be realized on the same FPGA with optimized throughput and accuracy. The proposed architecture is evaluated by implementing two different LeNet CNN models trained by different datasets and classifying different classes. Experimental results show that the implemented design achieves higher throughput than current LeNet FPGA accelerators.

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High Performance Accelerator for CNN Applications

Cited by 16 publications

References 7 publications

Automatic Deployment of Convolutional Neural Networks on FPGA for Spaceborne Remote Sensing Application

Automatic Deployment of Convolutional Neural Networks on FPGA for Spaceborne Remote Sensing Application

A dynamic discarding technique to increase speed and preserve accuracy for YOLOv3

Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration

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