High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

Suk, Sung Dae; Lee, Sung‐Young; Kim, Sung-Min; Yoon, Eunchul; Kim, Min Sang; Li, Ming; Oh, Chang Woo; Yeo, Kyongmin; Kim, Sung Hwan; Shin, Dongsuk D.; Lee, Kwan-Heum; Park, Heung Sik; Han, Jeorig Nam; Park, C.J.; Park, Jong-Bong; Kim, Dong-Won; Park, Donggun; Ryu, Byung-Il

doi:10.1109/iedm.2005.1609453

Cited by 108 publications

(24 citation statements)

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“…Figure 2a shows the simulated I d -V gs characteristics of 30 nm short channel cylindrical gate silicon nanowire MOSFET at V ds = 1.0 V and the transfer characteristics of extracted data of [30]. The results are in close proximity, thus validating the choice of models parameters taken in simulation.…”

Section: Calibrationmentioning

confidence: 62%

“…The calibration of model parameters used in the simulation has been performed according to the experimental results [30] using above-mentioned models. Figure 2a shows the simulated I d -V gs characteristics of 30 nm short channel cylindrical gate silicon nanowire MOSFET at V ds = 1.0 V and the transfer characteristics of extracted data of [30].…”

Section: Calibrationmentioning

confidence: 99%

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Influence of gate metal engineering on small-signal and noise behaviour of silicon nanowire MOSFET for low-noise amplifiers

Gupta

Chaujar

2016

Appl. Phys. A

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In this paper, we have investigated the smallsignal behaviour and RF noise performance of gate electrode workfunction engineered (GEWE) silicon nanowire (SiNW) MOSFET, and the results so obtained are simultaneously compared with SiNW and conventional MOS-FET at THz frequency range. This work examines reflection and transmission coefficients, noise conductance, minimum noise figure and cross-correlation factor. Results reveal significant reduction in input/output reflection coefficient and an increase in forward/reverse transmission coefficient owing to improved transconductance in GEWESiNW in comparison with conventional counterparts. It is also observed that minimum noise figure and noise conductance of GEWE-SiNW is reduced by 17.4 and 31.2 %, respectively, in comparison with SiNW, thus fortifying its potential application for low-noise amplifiers (LNAs) at radio frequencies. Moreover, the efficacy of gate metal workfunction engineering is also studied and the results validate that tuning of workfunction difference results further improvement in device small-signal behaviour and noise performance.

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Section: Calibrationmentioning

confidence: 62%

Section: Calibrationmentioning

confidence: 99%

Influence of gate metal engineering on small-signal and noise behaviour of silicon nanowire MOSFET for low-noise amplifiers

Gupta

Chaujar

2016

Appl. Phys. A

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“…One of the major reasons is that GAA design provides the best electrostatic integrity in comparison to all other different transistor architectures and therefore the best gate control over the channel [4,5]. However, in such ultra-scaled GAA transistors, the quantum mechanical effects play a significant role and they must be considered in order to obtain accurate results about the device performance [6][7][8].…”

Section: Intoductionmentioning

confidence: 99%

Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

Al-Ameri

Wang

Georgiev

et al. 2015

2015 IEEE Nanotechnology Materials and Devices Conference (NMDC)

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Abstract-This work investigates the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six various cross-section shapes. However all devices in the crosssectional area is kept constant in order to provide fair comparison between them. Additionally we expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we were able to obtain correlation between the mobile charge distributions in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs is also investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed mandatory for nanowires with such nano-scale dimensions.

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“…[1][2][3][4][5] In order to exploit the merit of NWFETs, the increase in the series resistance due to the small width of the source/drain (S/D) should be solved. An effective solution is to replace the conventional doped S/D with metallic materials.…”

Section: Introductionmentioning

confidence: 99%

Opening address

Ryazhskaya

2011

Phys.-Usp.

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We have found that the thermal history of the fabrication process of Si nanowires (NWs) has a strong impact on the Ni silicidation rate. We compared the Ni silicidation rates in Si NWs fabricated by two different types of processes: the "Doping First" process, in which dopant activation annealing is completed before the lithography of NW structures, and the "Patterning First" process, in which NWs are firstly fabricated and then subjected to heat treatment entailing thermal oxidation and dopant activation. The Ni silicidation rate was appreciably higher in the Doping First process than in the Patterning First process. The difference is attributed to the residual stress rather than to the dopant concentration in Si-NWs.To control the silicidation rate in NWs, particular attention to the thermal history is necessary.

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High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

Cited by 108 publications

References 1 publication

Influence of gate metal engineering on small-signal and noise behaviour of silicon nanowire MOSFET for low-noise amplifiers

Influence of gate metal engineering on small-signal and noise behaviour of silicon nanowire MOSFET for low-noise amplifiers

Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

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