High Performance 45nm CMOS Technology with 20nm Multi-Gate Devices

Krivokapić, Zoran; Tabery, Cyrus; Maszara, W.; Qi, Xiang; Lin, Ming-Ren

doi:10.7567/ssdm.2003.b-10-5l

Cited by 10 publications

(6 citation statements)

References 1 publication

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“…Bulk CoSi 2 WF values related to silicon midgap resulted. Devices with nickel silicide, [6][7][8][9][10][11][12][13][14][15][16][17] hafnium silicide, 18 platinum silicide, 19 and titanium silicide gates 16 were later reported. Using capacitors, Qin et al 6 were the first to demonstrate that the presence of dopant in polysilicon can affect gate WF upon full silicidation.…”

Section: Devices With Silicide Gatesmentioning

confidence: 99%

“…11 Advanced transistor with FUSI NiSi gate.-Excellent scalability of FUSI gate transistors with record-high drive currents has been demonstrated down to a 20 nm gate length. 10 Figure 4 shows a cross section of a FD SOI transistor with FUSI gate. FUSI gates on high-k dielectrics.-Several works have been recently published on FUSI gates on high-k dielectrics.…”

Section: Electrical Performance Of Nisi-gated Devicesmentioning

confidence: 99%

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Fully Silicided Metal Gates for High-Performance CMOS Technology: A Review

Maszara¹

2005

J. Electrochem. Soc.

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Full silicidation ͑FUSI͒ of polysilicon gates promises to be a simple approach for formation of metal gate electrodes for highly scaled complementary metal oxide semiconductor ͑CMOS͒ transistors. Devices have been reported with several different silicides, prominently with nickel. NiSi was shown to produce different work functions, covering a large portion of silicon bandgap, in relation to a dopant type and amount present in polysilicon. Elimination of polysilicon gate electrode depletion has been demonstrated. Data indicates that significant reduction of gate tunneling current is possible. A summary of developments of this new approach to metal gates and discussion of issues and challenges of the FUSI process and its applicability to highly scaled technologies is presented.Metal gates were a mainstay of metal oxide semiconductor ͑MOS͒ integrated circuits for many years until the need for denserpacked circuits brought about an end to aluminum gates and introduced a self-aligned approach afforded by polysilicon gate electrodes. Today, a comeback of metal gates is forecast in highperformance devices. Such gate electrodes deliver advantages of:No boron penetration from the polysilicon gate into channels through very thin gate dielectric, an increasingly difficult condition to maintain as gate dielectrics become thinner in scaled devices. Alternatively, a successful introduction of high-k dielectric could relax this constraint.Much lower gate resistance. Gate resistance-capacitance ͑RC͒ delay becomes a significant concern in designing circuits with very short gates.Desirable work function ͑WF͒ setting. Unlike polysilicon electrodes which have only two WFs available, one for n-channel MOS ͑n-MOS͒ and one for p-channel MOS ͑p-MOS͒, metal electrodes can set almost any WF for these devices. Specifically, a range of WFs from ϳ4.1 − 4.4 and ϳ4.8 − 5.1 eV would be attractive for n-MOS and p-MOS, respectively, for bulk and partially depleted silicon-on-insulator ͑PD SOI͒ transistors, and a range of WFs spanning almost the entire silicon bandgap could be utilized in fully depleted ͑FD SOI͒ devices, including FinFETs and Tri-gates.Perhaps the most desirable advantage of reduced electrical thickness of the gate dielectric ͑CET͒. Metal gates can fully eliminate depletion in heavily doped polysilicon gates ͑present in high vertical fields͒, which can amount to a 3-5 Å reduction in CET, the equivalent of a ϳtwo generation advancement.Metal gates have been realized in two general approaches: gatefirst and gate-last. The former approach retains the order of standard polysilicon gate process flow. Its main disadvantages are concerns about contamination of front-end tools during processing, particularly furnaces, difficult metal etching, and integrity of gate stack during high-temperature annealing. The gate-last approach is also called a replacement gate technique, where a dummy gate is removed after all doping and high-temperature processes are completed. Its main challenge is the dummy gate stack removal and replacement. Table I s...

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Section: Devices With Silicide Gatesmentioning

confidence: 99%

Section: Electrical Performance Of Nisi-gated Devicesmentioning

confidence: 99%

Fully Silicided Metal Gates for High-Performance CMOS Technology: A Review

Maszara¹

2005

J. Electrochem. Soc.

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“…The suppression of short-channel effects, therefore, is especially critical to enabling single-electron tunneling at elevated temperature in the scaled MOSFET. In this letter, we control the short-channel effect for devices with gate length down to 30 nm using thin oxide and multiple-gate SOI structures [9], [10]. Our device structure features nonoverlapped gate to source and drain.…”

Section: Introductionmentioning

confidence: 99%

An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

Lee

Chen

et al. 2006

IEEE Electron Device Lett.

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This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.Index Terms-CMOS, coulomb blockade oscillation, multiple gate, silicon-on-insulator (SOI), single-electron effect, single-electron transistor.

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“…For n-channel FinFET devices, the optimal gate work function Φ m lies between the midgap and the conduction band of Si, which necessitates the use Manuscript of the metal gates. It has been reported that a fully silicided metal gate can induce a strain in the transistor channel [2], and the localized strain could be exploited to enhance the performance of aggressively scaled transistors. While many approaches to strained Si have been reported, including the use of lattice-mismatched source and drain (S/D) regions [5], [6], high-stress capping layer [7], and poly-Si gate stressors [8], [9], strain introduction by a metal-nitride gate has not been experimentally reported.…”

Section: Introductionmentioning

confidence: 99%

Drive-Current Enhancement in FinFETs Using Gate-Induced Stress

Tan

Liow

Lee

et al. 2006

IEEE Electron Device Lett.

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A novel and simple process for the exploitation of metal-gate-induced stress in the Si channel region of a FinFET is reported. TaN metal-gate electrode was employed. The use of a silicon nitride capping layer, which covered the metal gate during the source and drain anneal, led to a large stress being developed as a result of the thermal-expansion coefficient mismatch between the gate and the capping layer. The resulting strain was retained and transferred to the Si channel. The stress introduced by the gate stressor was found to enhance the performance of the n-channel FinFETs and is believed to be tensile in the sourceto-drain direction. This approach may be applicable to other metal-gate materials having a mismatch in the thermal-expansion coefficient with surrounding capping materials.

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High Performance 45nm CMOS Technology with 20nm Multi-Gate Devices

Cited by 10 publications

References 1 publication

Fully Silicided Metal Gates for High-Performance CMOS Technology: A Review

Fully Silicided Metal Gates for High-Performance CMOS Technology: A Review

An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

Drive-Current Enhancement in FinFETs Using Gate-Induced Stress

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