High-mobility SiC MOSFET with low density of interface traps using high pressure microwave plasma oxidation*

Liu, Xinyu; Hao, Jilong; You, Nannan; Bai, Yun; Tang, Yidan; Yang, Chengyue; Wang, Shengkai

doi:10.1088/1674-1056/ab68c0

Cited by 10 publications

(6 citation statements)

References 34 publications

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“…Table 1 shows the key parameters used in simulations of this work. Channel mobility [13,14] (cm The parasitic body diode turns on at |V ds | ≈ 3.2 V and the MT MOS transfers to bipolar conduction mode with a sudden increase in the hole/total current. Therefore, the turn-on of the parasitic body diode is suppressed in the red shaded region.…”

Section: Structure and Mechanismmentioning

confidence: 99%

High performance SiC trench-type MOSFET with an integrated MOS-channel diode

Wang¹,

Jiang²,

Luo³

et al. 2023

Chinese Phys. B

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A novel SiC double-trench MOSFET with integrated MOS-channel diode is proposed and investigated by Sentaurus TCAD simulation. The new SiC MOSFET has a trench gate and a stepped-trench source, and features an integrated MOS-channel diode on the top sidewall of the source Trench (MT MOS). In the reverse conduction state, the MOS-channel diode turns on firstly to prevent the internal parasitic body diode being activated, and thus reduces the turn-on voltage (V F) and suppresses the bipolar degradation phenomena. The V F of 1.70V (@ I ds = -100 A/cm2) for the SiC MT MOS is 38.2% lower than that of SiC double-trench MOSFET (DT MOS). Meanwhile, the reverse recovery charge Q rr of the MT MOS is 58.7% lower than that of the DT MOS at I load = 700A/cm2, and thus the reverse recovery loss is reduced. Furthermore, owing to the modulation effect induced by the double trenches, the MT MOS preserves same superior forward conduction and blocking performance as those of DT MOS, with 22.9% and 18.2% improvement on BV and R ON,sp than the trench gate MOSFET with planar integrated SBD (ST MOS).

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Section: Structure and Mechanismmentioning

confidence: 99%

High performance SiC trench-type MOSFET with an integrated MOS-channel diode

Wang¹,

Jiang²,

Luo³

et al. 2023

Chinese Phys. B

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“…The vertically stacked horizontal gate-all-around (GAA) transistors are now established as the most promising candidate to the FinFETs in sub-5nm technology node, due to the excellent electrostatic and short channel control [ 1 , 2 , 3 ]. Moreover, to keep Moore’s Law alive as long as possible, researchers are also looking for alternatives to silicon channel material, like SiC, GaN, SiGe and Ge [ 4 , 5 , 6 , 7 ]. Among them, SiGe materials, especially those with Ge concentration between 20% and 40%, have been considered as the channel material of GAA devices.…”

Section: Introductionmentioning

confidence: 99%

4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process

Cheng

Zhao

et al. 2022

Nanomaterials

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In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si0.7Ge0.3 channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si0.7Ge0.3/Si film is achieved by optimizing the epitaxial growth process and a vertical profile of stacked Si0.7Ge0.3/Si fin is attained by further optimizing the etching process under the HBr/He/O2 plasma. Moreover, a novel ACT@SG-201 solution without any dilution at the temperature of 40 °C is chosen as the optimal etching solution for the release process of Si0.7Ge0.3 channel. As a result, the selectivity of Si to Si0.7Ge0.3 can reach 32.84 with a signature of “rectangular” Si0.7Ge0.3 extremities after channel release. Based on these newly developed processes, a 4-levels vertically stacked Si0.7Ge0.3 nanowires gate-all-around device is prepared successfully. An excellent subthreshold slope of 77 mV/dec, drain induced barrier-lowering of 19 mV/V, Ion/Ioff ratio of 9 × 105 and maximum of transconductance of ~83.35 μS/μm are demonstrated. However, its driven current is only ~38.6 μA/μm under VDS = VGS = −0.8 V due to its large resistance of source and drain (9.2 × 105 Ω). Therefore, a source and drain silicide process is implemented and its driven current can increase to 258.6 μA/μm (about 6.7 times) due to the decrease of resistance of source and drain to 6.4 × 104 Ω. Meanwhile, it is found that a slight increase of leakage after the silicide process online results in a slight deterioration of the subthreshold slope and Ion/Ioff ratio. Its leakage performance needs to be further improved through the co-optimization of source and drain implantation and silicide process in the future.

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“…[8][9][10] These defects can be eliminated by POA and improved oxidation processes; [5,[11][12][13] the latter can suppress the generation of these defects fundamentally by increasing the oxidant concentration near the SiC/silicon dioxide (SiO 2 ) interface. [14][15][16] Improved oxidation processes include wet oxidation, [17] NO oxidation, [6] plasma oxidation, [18,19] and ozone (O 3 ) oxidation. [20] Although these methods can reduce the interface trap density (D it ) of SiC MOS devices to some extent, wet oxygen, NO, and plasma oxidation may lead to V th /V fb instability, [21,22] the introduction of fast traps, [23] and sample damage due to highly energetic particle bombardment, [24] respectively.…”

Section: Introductionmentioning

confidence: 99%

Ozone oxidation of 4H-SiC and flat-band voltage stability of SiC MOS capacitors

et al. 2022

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We investigated the effect of ozone (O3) oxidation of silicon carbide (SiC) on the flat-band voltage (V fb ) stability of SiC metal-oxide-semiconductor (MOS) capacitors. SiC MOS capacitors were produced by O3 oxidation, and their V fb stability under frequency variation, temperature variation and bias temperature stress was evaluated. Secondary ion mass spectroscopy (SIMS), atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS) indicated that O3 oxidation can adjust the element distribution near SiC/SiO2 interface, improve SiC/SiO2 interface morphology and inhibit the formation of near-interface defects, respectively. In addition, we elaborated the underlying mechanism through which O3 oxidation improves the V fb stability of SiC MOS capacitors by using the measurement results and O3 oxidation kinetics.

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High-mobility SiC MOSFET with low density of interface traps using high pressure microwave plasma oxidation*

Cited by 10 publications

References 34 publications

High performance SiC trench-type MOSFET with an integrated MOS-channel diode

High performance SiC trench-type MOSFET with an integrated MOS-channel diode

4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process

Ozone oxidation of 4H-SiC and flat-band voltage stability of SiC MOS capacitors

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