High Level Synthesis of Complex Applications

Liu, Xinheng; Chen, Yao; Nguyen, Tan; Gurumani, Swathi; Rupnow, Kyle; Chen, Deming

doi:10.1145/2847263.2847274

Cited by 54 publications

(19 citation statements)

References 28 publications

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“…Achieved results are compared with Catapult C solution proposed in [1], and are better in terms of LUT resources used. Also implementation using Vivado HLS presented in [5] performs worse than the current solution in terms of achieved frame rate. On the other hand,…”

Section: Discussionmentioning

confidence: 88%

“…] claims it is able to decode macroblock in 5004 clock cycles. Implementation presented in[5] is also worse in terms of the frame rate, however it is complete H.264 decoder, both inter and intra-frame.…”

mentioning

confidence: 94%

“…Authors also described some language features applied, to increase implementation performance. [5] presented H.264 decoder written in Vivado HLS, claimed that its performance reaches 480p@34fps. This paper presents first known to authors, hardware implementation of CAVLC decoder in Impulse C language [7], and achieved results in terms of clock frequency, frame rate and resource usage.…”

Section: Introductionmentioning

confidence: 99%

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FPGA Implementation of H.264 CAVLC Decoder Using High-Level Synthesis

Cichoń

Gorgon

2017

Image Processing &Amp; Communications

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CONTEXT ADAPTIVE VARIABLE LENGTH CODING (CAVLC) is a method designed for coding residual pixel data after transform and quantization, in which different codes with variable length are chosen based on recently coded coefficients. Coded bitstream can be stored or transmitted. This method is optional in widely adopted H.264 video coding standard. The entire algorithm is a complex one, and also difficult to implement efficiently in Field-Programmable Gate Array (FPGA), due to data dependency. When the complexity of the Register Transfer Logic (RTL) implementation rises, it impacts the duration and costs of development. Therefore, usage of High Level Synthesis (HLS) may be beneficial with these types of projects. In this paper first known to authors implementation of CAVLC and Exp-Golomb decoders for H.264 intra decoder in Impulse C language will be presented and compared with other implementations. Proposed solution is able to decode more then 720p@40fps with FPGA module clock at 166MHz.

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Section: Discussionmentioning

confidence: 88%

mentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

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FPGA Implementation of H.264 CAVLC Decoder Using High-Level Synthesis

Cichoń

Gorgon

2017

Image Processing &Amp; Communications

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“…To help fully explore available resources of the targeted FPGAs, authors in [1] introduce an automatic resource allocation tool to generate fine-grained parallelism guidelines for its architecture. Researchers also employ High-level Synthesis (HLS) in their tools to improve design efficiency of FPGAbased hardware designs [31][32][33][34][35]. Figure 2: (a) The trends of DSP efficiency when running VGG16 with increasing input sizes in three representative FPGA-based DNN accelerators (batch size = 1); (b) Normalized throughput performance in three accelerators when running VGG-like DNNs with 3×224×224 inputs and 13∼38 CONV layers.…”

Section: Related Workmentioning

confidence: 99%

DNNExplorer

Zhang

Wang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…However, the conventional ways of writing hardware description language (HDL) code for FPGAs are both painful and take much longer time than code development on CPU/GPU. High-level synthesis (HLS), converting high-level language such as C, C++ to HDL automatically, largely mitigates the time-consuming FPGA code development process [9], [10], [11], [12], [13], [14], [15].…”

Section: Introductionmentioning

confidence: 99%

Efficient Methods for Mapping Neural Machine Translator on FPGAs

Zhang

Xiong³

et al. 2021

IEEE Trans. Parallel Distrib. Syst.

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Neural machine translation (NMT) is one of the most critical applications in natural language processing (NLP) with the main idea of converting text in one language to another using deep neural networks. In recent year, we have seen continuous development of NMT by integrating more emerging technologies, such as bidirectional gated recurrent units (GRU), attention mechanisms, and beam-search algorithms, for improved translation quality. However, with the increasing problem size, the real-life NMT models have become much more complicated and difficult to implement on hardware for acceleration opportunities. In this article, we aim to exploit the capability of FPGAs to deliver highly efficient implementations for real-life NMT applications. We map the inference of a large-scale NMT model with total computation of 172 GFLOP to a highly optimized high-level synthesis (HLS) IP and integrate the IP into Xilinx VCU118 FPGA platform. The model has widely used key features for NMTs, including the bidirectional GRU layer, attention mechanism, and beam search. We quantize the model to mixed-precision representation in which parameters and portions of calculations are in 16-bit half precision, and others remain as 32-bit floating-point. Compared to the float NMT implementation on FPGA, we achieve 13.1Â speedup with an end-to-end performance of 22.0 GFLOPS without any accuracy degradation. Based on our knowledge, this is the first work that successfully implements a real-life end-to-end NMT model to an FPGA on board.

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High Level Synthesis of Complex Applications

Cited by 54 publications

References 28 publications

FPGA Implementation of H.264 CAVLC Decoder Using High-Level Synthesis

FPGA Implementation of H.264 CAVLC Decoder Using High-Level Synthesis

DNNExplorer

Efficient Methods for Mapping Neural Machine Translator on FPGAs

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