High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures

Xydis, Sotirios; Pekmestzi, Kiamal; Soudris, Dimitrios; Economakos, George

doi:10.1109/isvlsi.2010.8

Cited by 2 publications

(3 citation statements)

References 9 publications

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“…Much research and development has been done into RC system design methodologies [5], [6], [7], [8]. The general synthesis flow in the RC system [9] is shown in Fig.…”

Section: Configuration Synthesis Algorithmmentioning

confidence: 99%

A circuit synthesis algorithm for coarse grained dynamic reconfigurable circuits

Araki

Kambe

2013

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)

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Reconfigurable Computing (RC) is a promIsmg paradigm that addresses the conflicting hardware design re quirements of high performance and area efficiency. Coarse grained architecture RC (CGA-RC) operates at the word level of granularity and exhibits better power and performance than fine-grained architectures. High level synthesis for Coarse-Grained Architecture Recon figurable Computing (CGA-RC) devices from high-level descrip tions is urgently needed to improve design efficiency. To realize this, it is also necessary to achieve both good performance and high PE (Processing Element) utilization automatically for all applications. In this paper, we address this issue by focusing on nested loop pipelining and hierarchical allocation of PEs and propose an algorithm to generate CGA-RC circuit configurations automatically. The methodology is compared with other methods to evaluate its performance.

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“…Much research and development has been done into RC system design methodologies [5], [6], [7], [8]. The general synthesis flow in the RC system [9] is shown in Fig.…”

Section: Configuration Synthesis Algorithmmentioning

confidence: 99%

A circuit synthesis algorithm for coarse grained dynamic reconfigurable circuits

Araki

Kambe

2013

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)

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“…The components (PE) in CGA systems are multifunctional and in order to make maximum use of this functionality it is important to use pipelining to speed up processing and to achieve high utilization of the PE components. Recently, several automatic design approaches for RC systems have been developed . However, interactive design is currently still the main approach.…”

Section: Introductionmentioning

confidence: 99%

“…Our research indicates that the key issues for the optimization of system LSI architecture at the design stage are parallelization, memory access, application specific circuit design, and module restructuring. …”

Section: Introductionmentioning

confidence: 99%

A Circuit Design Method for Dynamic Reconfigurable Circuits

Sawano

Kambe

2014

Elect Comm in Japan

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Summary Reconfigurable computing (RC) is a new paradigm that addresses the conflicting design requirements of high performance and high area density. Coarse‐grained architecture RC (CGA‐RC) operates at the word level of granularity and exhibits better power and performance features than fine‐grained architectures. However, in a CGA‐RC system, the processing elements (PE) implement several types of arithmetic operations and the routing between them has a fixed architecture. To achieve both good performance and high PE utilization for all applications, this paper proposes an interactive circuit design methodology for dynamically reconfigurable processors to accelerate their performance and achieve compact circuits. The method is applied to a JPEG encoder design and its performance evaluated.

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High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures

Cited by 2 publications

References 9 publications

A circuit synthesis algorithm for coarse grained dynamic reconfigurable circuits

A circuit synthesis algorithm for coarse grained dynamic reconfigurable circuits

A Circuit Design Method for Dynamic Reconfigurable Circuits

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