High-level synthesis hardware implementation and verification of HEVC DCT on SoC-FPGA

Mohamed, Belal; Elsayed, Amr; Amin, O.A.; Khafagy, Eslam; Abdelrasoul, Maher; Shalaby, Ahmed; Sayed, Mohammed S.

doi:10.1109/icenco.2017.8289815

Cited by 5 publications

(8 citation statements)

References 8 publications

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“…LUTs used by the 2D-IDCT/IDST is decreased by nearly 37% compared to [9]. Furthermore, our architecture does not use any DSP blocks as in [8] and [10]. The frame rate of the proposed 2D-IDCT/IDST represents enhancements of 25% compared to [10].…”

Section: Results Of the Iq/it Implementationmentioning

confidence: 99%

“…Furthermore, our architecture does not use any DSP blocks as in [8] and [10]. The frame rate of the proposed 2D-IDCT/IDST represents enhancements of 25% compared to [10]. On the other hand, not only does our IQ/IT hardware architecture use about 47% of the LUTs, but it also employs only 2% and 1% of the available DSPs and block RAMs, respectively.…”

Section: Martuza Et Al [4]mentioning

confidence: 99%

“…In the worst of cases, this architecture can process 4K at 48 fps. Finally, in [10], Mohamed et al provide a system-on-chip FPGA platform based on Xilinx Zynq to integrate the DCT coding block as an accelerator. The proposed design is capable to perform the coding of 1080 at 30 fps.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

Atitallah¹,

Kammoun²,

Atitallah³

2020

Turk J Elec Eng & Comp Sci

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This paper presents an optimized hardware architecture of the inverse quantization and the inverse transform (IQ/IT) for a high-efficiency video coding (HEVC) decoder. Our highly parallel and pipelined architecture was designed to support all HEVC Transform Unit (TU) sizes: 4 × 4, 8 × 8, 16 × 16 , and 32 × 32. The IQ/IT was described in the VHSIC hardware description language and synthesized to Xilinx XC7Z020 field-programmable gate array (FPGA) and to TSMC 180 nm standard-cell library. The throughput of the hardware architecture reached in the worst case a processing rate of up to 1080 p at 33 fps at 146 MHz and 1080 p at 25 fps at 110 MHz when mapped to FPGA and standardcells, respectively. The validation of our architecture was conducted on the ZC702 platform using a Software/Hardware (SW/HW) enviro nment in order to evaluate different implementation methods (SW and SW/HW) in terms of power consumption and run-time. The experimental results demonstrate that the SW/HW accelerations were enhanced by more than 70% in terms of the run-time speed relative to the SW solution. Besides, the power consumption of the SW/HW designs was reduced by nearly 60% compared with the SW case.

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Section: Results Of the Iq/it Implementationmentioning

confidence: 99%

Section: Martuza Et Al [4]mentioning

confidence: 99%

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An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

Atitallah¹,

Kammoun²,

Atitallah³

2020

Turk J Elec Eng & Comp Sci

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“…A step further was taken with massive parallelization in [9] and all functional blocks of HEVC decoder, except entropy decoder, were ported to GPU. Quite the contrary, solutions with TQ acceleration using FPGAs rather than the GPU [10] are much more represented as a research topic.…”

Section: Related Work and Motivationmentioning

confidence: 99%

Performance engineering for HEVC transform and quantization kernel on GPUs

et al. 2020

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Continuous growth of video traffic and video services, especially in the field of high resolution and high-quality video content, places heavy demands on video coding and its implementations. High Efficiency Video Coding (HEVC) standard doubles the compression efficiency of its predecessor H.264/AVC at the cost of high computational complexity. To address those computing issues high-performance video processing takes advantage of heterogeneous multiprocessor platforms. In this paper, we present a highly performance-optimized HEVC transform and quantization kernel with all-zero-block (AZB) identification designed for execution on a Graphics Processor Unit (GPU). Performance optimization strategy involved all three aspects of parallel design, exposing as much of the application's intrinsic parallelism as possible, exploitation of high throughput memory and efficient instruction usage. It combines efficient mapping of transform blocks to thread-blocks and efficient vectorized access patterns to shared memory for all transform sizes supported in the standard. Two different GPUs of the same architecture were used to evaluate proposed implementation. Achieved processing times are 6.03 and 23.94 ms for DCI 4K and 8K Full Format, respectively. Speedup factors compared to CPU, cuBLAS and AVX2 implementations are up to 80, 19 and 4 times respectively. Proposed implementation outperforms previous work 1.22 times.

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“…The developed design can decode 54 frames/sec (FPS) for 1080p video sequences. In [24], the authors provide a System-On-Chip FPGA platform based on Xilinx Zynq to integrate the DCT coding block as an accelerator with HLS tool. The proposed design is capable to perform the coding of 1080@30fps.…”

Section: Introductionmentioning

confidence: 99%

Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules

Alanazi¹,

Atitallah²

2022

Computers, Materials &Amp; Continua

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As the newest standard, the High Efficiency Video Coding (HEVC) is specially designed to minimize the bitrate for video data transfer and to support High Definition (HD) and ULTRA HD video resolutions at the cost of increasing computational complexity relative to earlier standards like the H.264. Therefore, real-time video decoding with HEVC decoder becomes a challenging task. However, the Dequantization and Inverse Transform (DE/IT) are one of the computationally intensive modules in the HEVC decoder which are used to reconstruct the residual block. Thus, in this paper, a unified hardware architecture is proposed to implement the HEVC DE/IT module for all Transform Unit (TU) block size, including 4 × 4, 8 × 8, 16 × 16 and 32 × 32. This architecture is designed using the High-Level Synthesis (HLS) and the Low-Level Synthesis (LLS) methods in order to compare and determine the best method to implement in real-time the DE/IT module. In fact, the C/C++ programming language is used to generate an optimized hardware design for DE/IT module through the Xilinx Vivado HLS tool. On the other hand, the LLS hardware architecture is designed by the VHSIC Hardware Description language (VHDL) and using the pipeline technique to decrease the processing time. The experimental results on the Xilinx XC7Z020 FPGA show that the LLS design increases the throughput in term of frame rate by 80% relative to HLS design with a 4.4% increase in the number of Look-Up Tables (LUTs). Compared with existing related works in literature, the proposed architectures demonstrate significant advantages in hardware cost and performance improvement.

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High-level synthesis hardware implementation and verification of HEVC DCT on SoC-FPGA

Cited by 5 publications

References 8 publications

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

Performance engineering for HEVC transform and quantization kernel on GPUs

Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules

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