High-level optimization of integer multipliers over a finite bit-width with verification capabilities

Logic synthesis and circuit customization using extensive external don't-cares

“…This shallow logic structure makes signal sharing difficult. Case study 2 (constant-coefficient multiplier): embedded systems and digital signal processors often need to perform simple operations repetitively [Lai et al 2008;Sarbishei et al 2009]. For example, consider a portable electronic measurement device that must convert between US units and metric units while keeping power consumption low.…”

“…This is because SWEDE is unconcerned with the complexity of the original functionality and can focus on just a few important inputs for its optimization. This characteristic makes SWEDE considerably different from domain-specific optimization techniques such as [Sarbishei et al 2009] in that our methods do not require architectural information. To further study the behavior of the specialized multiplier, we computed all the multiplications where one input ranges from 0 to 65535, and the other from 100 to 199, producing a total of 6553600 input combinations.…”

Optimization of modular multiplication on FPGA using don't care conditions

“…It makes use of word-level don't care conditions to generate minimized multi-level logic nodes that should be mapped into LUTs. Although the optimization technique in [1] only targeted Application Specific Integrated Circuit (ASIC) designs while the goal is literal count minimization, this paper concentrates on LUT-based optimization of modular arithmetic circuits to reduce resource consumption when mapping into LUT-based FPGA.…”