High-level modeling of resistor string based digital-to-analog converters

Abstract

To obtain a high performance CMOS resistor string digital-to-analog converter (DAC), one of the key design issues is the mismatch in the resistor ratio. This mismatch causes nonlinearity errors such as integral nonlinearity (INL) and differential nonlinearity (DNL), degrading the performances of the converter. Usually these matching properties are taken into account during the design phase by using time consuming and computational intensive transistor-level Monte Carlo simulations for the process technology corner. Recent research aims at reducing the design time by exploiting high-level modeling of converters as a trade-off between simulation time and modelling accuracy. In this work an analytical model for resistor mismatch in DACs is presented and implemented in MATLAB (TM) environment. The model utilizes geometrical size of resistors and statistical data of the technology process. Starting from random process variations on geometries it was possible to estimate DNL and INL with very short time simulations. The proposed model is valid both for single stage resistor string DACs or segmented ones. The model can be used to speed up the design of resistor-string based DACs, or as a starting point to develop more accurate models by taking into account high-order effects. The model was successfully used to design a 10bit resistor string DAC in a 0.18 mu m BCD technology with DNL and INL lower than 1 LSB (in absolute value). Since the complexity of the DAC is dominated by the resistor string, its optimization since the early design steps, enabled by the proposed high-level model, allowed to minimize area versus state of the art

Slew-rate Boosted Amplifier Integrated in a Digital Input Driver for Automotive Actuator Control Units

“…1 exploits the resistor string based architecture originally proposed by us in [4]. In this work the design has been optimized for 10 bits; non linearity values, INL and DNL, below 1 LSB are obtained (about 0.7 LSB in typical conditions).…”

A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation

“…At the state of the art the resistor-string sizing is often done a priori or after comparisons by transistor-level simulations of few sizing alternatives, since transistor-level simulations are too time consuming. On the contrary, in this work we use a previously developed [14] high-level model of resistor-divider-based DACs, much faster than transistor-level simulations, to find a trade-off between good performances on nonlinearities (such as DNL and INL) and area occupation. As an example of the considered BCD technology and 10-bit resolution specifications Figure 4 shows how σ ΔR/R (which is a resistorstring mismatch parameter directly proportional to DNL and INL) varies verus resistor size W and L. The plot, that depicts the behavior of σ ΔR/R versus resistor length (L), is parametrized with W, the resistor width.…”