2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) 2021
DOI: 10.1109/ipdps49936.2021.00117
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High-Level FPGA Accelerator Design for Structured-Mesh-Based Explicit Numerical Solvers

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Cited by 4 publications
(20 citation statements)
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References 27 publications
(30 reference statements)
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“…The Rannacher smoothing available in the original application has been switched off in our evaluation. The hv_pred* and hv_matrices are explicit loops each using 10 point stencils, requiring a window buffer implementation [13] for data reuse. The 9 kernels in Algo.…”
Section: Stochastic Local Volatilitymentioning
confidence: 99%
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“…The Rannacher smoothing available in the original application has been switched off in our evaluation. The hv_pred* and hv_matrices are explicit loops each using 10 point stencils, requiring a window buffer implementation [13] for data reuse. The 9 kernels in Algo.…”
Section: Stochastic Local Volatilitymentioning
confidence: 99%
“…In comparison, the HLS-based synthesis presented in this paper, targets the solution of multiple tridiagonal systems and in multiple dimensions as commonly found in real-world applications. It uses the Thomas algorithm demonstrating that together with techniques such as batching of systems [13], high throughput for small and medium sized systems can be achieved. The Thomas algorithm uses fewer resources than the more computationally intensive PCR algorithm.…”
Section: Related Workmentioning
confidence: 99%
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“…Field Programmable Gate Arrays (FPGAs) have gained traction as accelerator devices, particularly due to their low power consumption and re-programmability. Their utility in accelerating scientific computing workloads have recently been gaining interest in the high performance computing (HPC) community with several studies showing competitive or better performance compared to traditional CPU/GPU architectures, for select classes of applications [9,13,19,27].…”
Section: Introductionmentioning
confidence: 99%
“…(1) Based on design strategies developed in previous work [19,20], in this paper we develop a generalized workflow for formulating optimized FPGA designs with SYCL, targeting Intel FPGAs for two classes of structured-mesh based solvers: (1) stencil applications based on explicit numerical methods and…”
Section: Introductionmentioning
confidence: 99%