High-level delay estimation for technology-independent logic equations

Wallace, David E.; Chandrasekhar, M. S.

doi:10.1109/iccad.1990.129876

Cited by 19 publications

(8 citation statements)

References 4 publications

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“…The power estimates were obtained using random simulation with 100 000 input vectors. To take into account the impact of increased circuit area on the switched capacitance, and since at this level of abstraction no detailed routing information is available, we used a standard wire load model [15] in the computation of line capacitance. In this manner, we take into account the impact of the increase in area of the decomposed circuit in the overall power consumption.…”

Section: Resultsmentioning

confidence: 99%

Implicit FSM decomposition applied to low-power design

Monteiro

Oliveira

2002

IEEE Trans. VLSI Syst.

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Section: Resultsmentioning

confidence: 99%

Implicit FSM decomposition applied to low-power design

Monteiro

Oliveira

2002

IEEE Trans. VLSI Syst.

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“…Previous works have been done to estimate the circuit delay given a Boolean function [8,9]. [10] gives a comprehensive survey on this issue.…”

Section: Delay Modelmentioning

confidence: 99%

“…However, this is not always true when the effect of the capacitive loading on the circuit delay is taken into consideration. If we focus only on the fanout optimization problem which tries to drive a certain fanout loading with a minimum delay, the delay can be modeled as a logarithmic function of the load capacitance, as explained in [9]. Based on these observations, we model the delay of the MDI of a circuit using the following equation…”

Section: Delay Modelmentioning

confidence: 99%

Towards the capability of providing power-area-delay trade-off at the register transfer level

Chen

Tsui

1998

Proceedings of the 1998 International Symposium on Low Power Electronics and Design - ISLPED '98

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This paper presents a new register-transfer level (RTlevel) power estimation technique based on technology decomposition. Given the Boolean description of a circuit function, the power consumption of two typical circuit implementations, namely the minimum area implementation and the minimum delay implementation, are estimated, respectively. This provides a capability of obtaining a full power-delay-area trade-off curve at the RT level. Our method makes it possible to capture the structural and/or functional information of a circuit without going through actual gate-level implementation. Experimental results show that the accuracy is very reasonable. KeywordsRT-level, power estimation, entropy, technology decomposition INTRODUCTIONPower reduction has become one of the primary goals in the design of modern digital systems due to the increasing demand for low power circuits in portable applications. Increasing package and cooling cost is another driving factor. To achieve low power design, the designer has to explore the design space to make the appropriate powerarea-delay trade-off decision. Accurate power estimation at different abstraction levels is thus urgently needed to carry out the correct design space exploration.Recently several RT level power estimation methodologies were proposed based on entropy and information theoretic approaches [1,2]. However, these approaches are suffering from two main discrepancies. First, entropy of the function of the circuit is used to estimate the circuit switching activity as well as to model the area cost of a circuit [2][3][4]. Unfortunately, the accuracy of entropy-based power estimation is very limited since the capacitance model using entropy does not work well over a wide range of circuits. Secondly, these methods only give a single power estimate for a given functional description of the circuit. They use very little information about the function and complexity of the circuit at the behavioral level and also do not account for the effect of different potential circuit implementations for different requirements. In this paper, we are targeting to provide a capability to generate the power-area-delay tradeoff curve at the RT level. In particular, we propose a method to estimate the power consumption for the minimum area implementation (MAI) and the minimum delay implementation (MDI) given a functional description of a circuit. These are the two extreme points of the power-areadelay trade-off curve whose power estimation serves as a first step to generate the full trade-off curve.The remainder of the paper is organized as follows. In Section 3, we describe the power estimation technique for the MAI based on technology decomposition. We discuss the modeling of node distribution, capacitance distribution as well as entropy distribution for power estimation. Section 4 is devoted to the power estimation for the MDI, including the method of estimating the delay and the total capacitance for the MDI. Experimental results and discussions are provided in Section 5 and, ...

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“…The delay model introduced by Wallace et al [1990] estimates the complexity of a node with a formula based on the decomposition of the logic expression of the node onto a minimum-height tree. An unmapped node in the network is stored in sum-of-products form.…”

Section: Approximate Timing Delay Modelsmentioning

confidence: 99%

Retiming-based factorization for sequential logic optimization

Bommu

O'Neill²,

Ciesielski

2000

ACM Trans. Des. Autom. Electron. Syst.

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Current sequential optimization techniques apply a variety of logic transformations that mainly target the combinational logic component of the circuit. Retiming is typically applied as a postprocessing step to the gate-level implementation obtained after technology mapping. This paper introduces a new sequential logic transformation which integrates retiming with logic transformations at the technology-independent level. This transformation is based on implicit retiming across logic blocks and fanout stems during logic optimization. Its application to sequential network synthesis results in the optimization of logic across register boundaries. It can be used in conjunction with any measure of circuit quality for which a fast and reliable gain estimation method can be obtained. We implemented our new technique within the SIS framework and demonstrated its effectiveness in terms of cycle-time minimization on a set of sequential benchmark circuits.

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High-level delay estimation for technology-independent logic equations

Cited by 19 publications

References 4 publications

Implicit FSM decomposition applied to low-power design

Implicit FSM decomposition applied to low-power design

Towards the capability of providing power-area-delay trade-off at the register transfer level

Retiming-based factorization for sequential logic optimization

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