High Level - Application Analysis Techniques &amp;amp; Architectures - To Explore Design possibilities for Reduced Reconfiguration Area Overheads in FPGAs executing Compute Intensive Applications

Dasu, Aravind; Sudarsanam, Arvind

doi:10.1109/ipdps.2005.242

Cited by 8 publications

(5 citation statements)

References 8 publications

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“…There have also been efforts to use common subgraph detection methods for the purpose of discovering hard-cores for FPGAs [9], which presents a methodology from the point of view of reducing area and configuration overheads. However, in this paper we present, for the first time, a quantitative analysis of possible components identified by common subgraph extraction, including a comparison of their speeds and areas in both FPGA and ASIC for 90nm technology.…”

Section: Introductionmentioning

confidence: 99%

Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction

Smith

Constantinides

Cheung

2007

2007 International Conference on Field-Programmable Technology

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Abstract-To complement the flexible, fine-grain logic in Field Programmable Gate Arrays (FPGAs), configurable hardware devices now incorporate more complex coarse-grain components such as memories, embedded processing units and fusedarithmetic units. These components provide speed and density advantages due to the specialised logic and fixed interconnect. In this paper, a methodology is presented to automatically propose and explore the benefits of different types of fused arithmetic units for configurable devices. The methods are based on common subgraph extraction techniques, meaning that it is possible to explore different subcircuits that occur frequently across a set of benchmarks. A quantitative analysis is performed of the various fused-arithmetic circuits identified by our tool, which are then automatically synthesised to an ASIC process, providing a study of the speed and area benefits of the components. We report improvements of up to 3.3× in speed and 19.7× in area for the average improvement of particular silicon cores identified by our approach when compared to implementation of the same subcircuits implemented in a commercial mixed-granularity FPGA in a comparable 90nm technology. The average improvements across all embedded cores identified by our approach are 1.67× and 5.55× when designing the ASIC cores for fastest speed performance.

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Section: Introductionmentioning

confidence: 99%

Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction

Smith

Constantinides

Cheung

2007

2007 International Conference on Field-Programmable Technology

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“…However they can not exploit the multiplexers already contained in the datapaths. Aravind et al [6] investigate a method to extract a common subgraph from several tasks and implement the common subgraph as a static datapath. The other parts of the tasks are mapped to the reconfigurable fabric.…”

Section: Related Workmentioning

confidence: 99%

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs

Rullmann

Merker

Hinkelmann

et al. 2009

2009 International Conference on Field Programmable Logic and Applications

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Efficient cycle-based reconfiguration of datapaths can be realized on current FPGAs by designing merged datapaths, which can execute different tasks depending on the datapath control. In our previous work, we provided a synthesis tool for the automated generation of such datapaths. The objective in this paper is a reduction of the resource requirements for implementing the reconfiguration control on the FPGA. First, we extend our existing tool flow with a novel mechanism for efficient partial multi-context reconfiguration and provide tool support to generate according circuitry, control, and configuration data. Second, we propose an extension of current FPGA architectures to efficiently support cycle-based runtime control. We employ a special contentaddressable multi-context memory resource for controlling the datapath functionality, which on average requires only 15 % memory for storing the control data compared to a BlockRAM based approach, and only 53 % compared to regular multi-context switching.

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“…To obtain an energy efficient design for FFT, we analyze the tradeoffs between energy, area, and time for fixed-point FFT on a parameterized architecture, using Cooley-Tukey algorithm. Energy efficiency can be obtained both at the algorithm mapping level and the architecture level [7,8]. Optimizing at these two levels allows power to be effectively traded off with other performance parameters.…”

Section: Introductionmentioning

confidence: 99%

Energy efficient parameterized FFT architecture

Ren

Prasanna

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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Recently, there has been a growing interest within the research community to improve energy efficiency. In this paper, we revisit the classic Fast Fourier Transform (FFT) for energy efficient designs on FPGAs. Parameterized FFT architecture is proposed to identify design trade-offs in achieving energy efficiency. We first perform design space exploration by varying the algorithm mapping parameters, such as the degree of vertical and horizontal parallelism, that characterize the decomposition based FFT algorithms. After empirical selection on the values of algorithm mapping parameters, an energy-performance-area trade-off design for energy efficiency is identified by varying the architecture parameters, including the type of memory elements, the type of interconnection network and the number of pipeline stages. The tradeoffs between energy, area, and time are analyzed using two performance metrics: the Energy×Area×Time (EAT) composite metric and the energy efficiency (defined as the number of operations per Joule). From the experimental results, a design space is generated to demonstrate the effect of these parameters on the various performance metrics. For N -point FFT (16 ≤ N ≤ 1024), our designs achieve up to 28% and 38% improvement in the energy efficiency and EAT, respectively, compared with a state-of-the-art design.

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High Level - Application Analysis Techniques & Architectures - To Explore Design possibilities for Reduced Reconfiguration Area Overheads in FPGAs executing Compute Intensive Applications

Cited by 8 publications

References 8 publications

Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction

Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs

Energy efficient parameterized FFT architecture

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