High-k/metal gate stacks in gate first and replacement gate schemes

Kesapragada, Sree; Wang, Rongjun; Liu, Dave; Liu, Guojun; Xie, Zhigang; Ge, Zhong; Yang, Hui; Lei, Yu; Lu, X.; Tang, Xianmin; Lei, Jianxin; Allen, M.D.; Gandikota, Srinivas; Moraes, Kevin; Hung, Steven; Yoshida, N.; Chang, Chorng‐Ping

doi:10.1109/asmc.2010.5551460

Cited by 13 publications

(9 citation statements)

References 5 publications

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“…(1) Based on the accumulation of the experimental data, the industry has found the high-κ/metal gate solution for the planar CMOSFETs, with ALD HfO 2 as the gate dielectric, PVD TiAl as the n-type metal gate and PVD TiN as the p-type metal gate, in a replacement gate process. The successful development of the dual metal gate technology seems to originate from the encouraging C-V measurement results by Kesapragada et al [45], showing a 1 V separation between the MOSCAP using PVD TiAl and PVD TiN. (2) The ALD of the three element metal candidates, Ru, Pt and W, has attracted much attention.…”

Section: Discussionmentioning

confidence: 99%

“…As mentioned before, the first industrial high-κ/metal gate technology for 45 nm node, reposted in 2007, used TiAl alloy as n-type MOSFETs [25]. The capacitor using AlTi n-type metal and HfO 2 showed an ideal C-V curve and n-type EWF [45]. In all the above works, the n-type metal gate were deposited by PVD.…”

Section: Ald Of N-type Metal Gatementioning

confidence: 99%

“…Alloying Al into more refractory metal to form alloy was one of the research directions [43]. Doping Al into PVD TiN, for example, can shift the EWF from the value near the bottom of the Si conduction band to that near the top of the valence band [44] [45]. Intel seemed to use this combination for their planar CMOS integration, and got working high-performance devices with large gate leakage current reduction [25].…”

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confidence: 99%

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Atomic Layer Deposition (ALD) of Metal Gates for CMOS

Zhao

Xiang

2019

Applied Sciences

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The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

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Section: Discussionmentioning

confidence: 99%

Section: Ald Of N-type Metal Gatementioning

confidence: 99%

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confidence: 99%

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Atomic Layer Deposition (ALD) of Metal Gates for CMOS

Zhao

Xiang

2019

Applied Sciences

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“…Finally, an aluminum layer was deposited; this layer was defined as a FP by the mask. (HKMG) stacks can reduce the gate leakage and eliminate the poly-gate depletion [37][38][39]. A 250-nm thick tetra-ethyl-ortho-silicate (TEOS) oxide was deposited followed by chemical-mechanical polishing to planarize the top surface.…”

Section: Methodsmentioning

confidence: 99%

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

Zeng

Chen

2018

Applied Sciences

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Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage. The GIDL of fin-like TFTs (FinTFTs) examined in this study was dominated by longitudinal band-to-band tunneling (L-BTBT). Extending the wide drain can effectively suppress the longitudinal electric field near the drain and improve L-BTBT GIDL and breakdown. In addition, a wider drain can lead to a large cross section in the current path and improve the ON-state current. FinTFTs with wide drain exhibit a low GIDL, a high ON-state current, and high breakdown voltage, while maintaining favorable gate controllability.

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“…[7][8][9] For integrating the metal gate as well as the high-K gate oxide, the gate last or replacement metal gate (RMG) scheme is widely used. [10][11][12][13] During this process, the gate is initially fabricated with a dummy material (generally poly-Si), which is later etched off and filled with the appropriate gate metal. 14 Scaling to a gate length (L gate ) of ∼30 nm has been successfully achieved using Al as the gate material.…”

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confidence: 99%

Role of Potassium Permanganate-Based Solutions in Controlling the Galvanic Corrosion at Al-Co Interface

Lagudu

Chockalingam

Eckonomikos³

et al. 2013

ECS J. Solid State Sci. Technol.

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Al-Co metal gate has been recently proposed both for 25 and 11 nm devices as an alternative for Al-Ti used for 45 nm structures. The polishing dispersions used for Al-Ti gates when tested on Al-Co showed severe pitting and static etch rates upto ∼10 nm/min. The present work describes the development of the required chemistry to reduce the corrosion potential (E corr ) gap between Al and Co and minimize galvanic corrosion. The effect of pH, several oxidizers and additives on the open circuit potentials (E oc ) of Al and Co was investigated and it was discovered that solutions of KMnO 4 and saccharides help reduce the E corr gap in between Al and Co to ∼10 mV. A preliminary corrosion protection mechanism involving the formation of a protective manganese oxide coating on the surface of Al/Co is proposed.Reduction of SiO 2 gate oxide thickness and length has been crucial to the continued scaling down of CMOS devices and obtain performance gain. For example, the 90 nm node had a gate oxide thickness between 8-12 Å. 1,2 In 32 nm devices, a further reduction in the gate oxide thickness is needed but was not possible due to the associated increase in leakage current. 3-6 A combination of high-K dielectric gate film with an appropriate metal gate has effectively solved the problem, as was shown by several authors. [7][8][9] For integrating the metal gate as well as the high-K gate oxide, the gate last or replacement metal gate (RMG) scheme is widely used. 10-13 During this process, the gate is initially fabricated with a dummy material (generally poly-Si), which is later etched off and filled with the appropriate gate metal. 14 Scaling to a gate length (L gate ) of ∼30 nm has been successfully achieved using Al as the gate material. 15 A suitable wetting layer, usually Ti, is needed to flow the Al into and fill the trench vacated by the dummy gate during the RMG process. A typical structure is shown in Fig. 1. However, for L gate < 25 nm, after the poly open CMP, Ti deposited using physical vapor deposition (PVD) is reported 15 to exhibit overhangs at the top of the gate which would retard the flow of Al into the open space. Kwon et al., 16 at IBM, have very recently developed a novel cobalt-aluminum-based metal fill scheme in the replacement metal gate (RMG) process that can be scaled down to 11 nm. Using Co instead of Ti improved the flow of Al into the high aspect ratio trench as well as maintained the desired electrical properties of the gate.One of the challenges of this strategy is that Co and Al in contact with each other in an aqueous medium during a chemical mechanical planarization (CMP) step would form a galvanic couple due to their high (>1V) open circuit potential (E oc ) difference. Galvanic corrosion can occur when two metals with such a large E oc difference contact with each other within the device architecture and are exposed to charge conducting CMP slurries. Al acts as the anode and corrodes faster in the presence of Co as its standard electrode potential (E • = −1.66 V) is low compared to that of Co (...

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High-k/metal gate stacks in gate first and replacement gate schemes

Cited by 13 publications

References 5 publications

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

Role of Potassium Permanganate-Based Solutions in Controlling the Galvanic Corrosion at Al-Co Interface

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