High interfacial quality metal-oxide-semiconductor capacitor on (111) oriented 3C-SiC with Al₂O₃ interlayer and its internal charge analysis

Abstract

Metal-oxide-semiconductor (MOS) capacitors with various gate dielectrics were fabricated on (111) oriented n-type 3C-SiC. Deposited SiO2 by sputtering without an interlayer (IL) and thermally grown SiO2 show deteriorated capacitance–voltage (C–V) characteristics and high interface trap density (Dit) over 1011–1012 cm−2 eV−1. By inserting an IL, C–V and leakage current characteristics are improved. In particular, an atomic layer deposited (ALD) Al2O3-IL is suitable for 3C-SiC, which successfully achieved low Dit in the order of 1010 cm−2 eV−1. MOS capacitor with the same gate dielectric on n-Si shows contradictory characteristics. Structural analysis shows it is considered the flat and uniform interface at Al2O3/3C-SiC leads good electrical characteristics. The 3C-SiC MOS capacitor with Al2O3-IL showed slightly negative flatband voltage and it is induced by negative interfacial dipole generated at the Al2O3/3C-SiC interface. This 3C-SiC MOS structure can be fabricated at low process temperature (<600 °C), which means the overall process for device application can be designed more flexibly.

High channel mobility of 3C-SiC n-MOSFETs with gate stacks formed at low temperature—the importance of Coulomb scattering suppression

“…© 2022 The Japan Society of Applied Physics listed the D it values of the MOS capacitors calculated using a high and low-frequency C-V (high-low) method in our former study, and the magnitude correlation is the same as the result from SS. 16) It should be noted that D it values evaluated from SS are 10-30 times higher than those from the high-low method for both gate stacks. It is a common phenomenon for SiC gate stacks, and the reason is the underestimation (better than the actual value) of the high-low method.…”

“…As an alternative method, we have succeeded in fabricating 3C-SiC MOS capacitors using sputter-deposited SiO 2 /plasma oxidized interlayer (plasma oxi.-IL) and SiO 2 /Al 2 O 3 -IL. 16) The process temperature is as low as about 500 °C, and we achieved outstanding C-V characteristics with low D it and narrow hysteresis. This low-temperature process is preferable for the on-chip hetero-integration between Si and 3C-SiC.…”

“…Here, D it (high-low), Q fix , and δ dipole for #3 are from our former study in Ref. 16. D it (high-low) is the average value in the trap energy range of…”

“…Next, S/D activation annealing was performed at 1200 °C in N 2 ambient for 2 h. After substrate cleaning by the RCA method, three kinds of gate stacks were formed. 16) For sample #1, thermally oxidized SiO 2 was grown in dry O 2 at 1200 °C, following N 2 annealing at 1200 °C. For sample #2, ECR plasma oxi.-IL was grown, and a ∼30 nm thick SiO 2 was deposited using ECR plasma sputtering without breaking the vacuum.…”

AlGaN/GaN HEMT on 3C-SiC/Low-Resistivity Si Substrate for Microwave Applications

“…So far, it has been reported that a stable 3C-SiC intermediate layer can be introduced in between GaN and Si to suppress the crack generation and enhance the crystal quality of the GaN film on Si substrate [14], [17]- [20]. Owing to the above fact, a thick nitride layer can be grown on Si by introducing a 3C-SiC intermediate layer [14], [20].…”