A 60 GHz power amplifier (PA) based on a 28 nm CMOS technology is presented for WiGig applications. It consists of a two-stage pseudodifferential common-source structure using low-power and low-V t transistors, capacitive neutralisation for isolation enhancement and integrated transformers for impedance matching, power splitting, power combining and balanced-to-unbalanced transformation purposes. The output-stage transistors have a measured 1 dB output compression point (OCP 1 dB ) of 10.2 dBm, a 10.2 dB gain and a peak power added efficiency (PAE) as high as 35%. The fabricated PA achieves a 12 dBm OCP 1 dB , a 15.3 dB gain and a peak PAE better than 20% while occupying a silicon active area of only 0.037 mm 2 .Introduction: Recent advances in silicon-based technologies along with a demand for high-speed wireless connections have driven the development of wireless local area networks (WLANs) standards operating at 60 GHz such as WiGig [1]. Such applications require a low-cost and low-power implementation, which favours the adoption of system-on-chip implementations for the transceivers. Therefore, owing to the large amount of digital circuitry integrated in such systems, the use of advanced CMOS nodes becomes the most suitable technology choice. Nevertheless, the use of downscaled processes poses a number of challenges in the design of analogue and RF blocks. Namely, for the design of power amplifiers (PAs), the low breakdown voltage makes it increasingly difficult to obtain high-output power levels. Moreover, as the back-end-of-line of the technologies is scaled, passive devices tend to become increasingly lossy. This Letter presents the design of a 28 nm CMOS PA targeting WiGig applications in the 60 GHz band.