High frequency n-type MODFETs on ultra-thin virtual SiGe substrates

Hackbarth, T.; Herzog, H.‐J.; Rinaldi, F.; Soares, Thiago R. B. S.; Holländer, B.; Mantl, S.; Luysberg, M.; Fichtner, P.F.P.

doi:10.1016/s0038-1101(03)00035-2

Cited by 11 publications

(7 citation statements)

References 8 publications

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“…One of the most exciting new techniques for virtual substrates was demonstrated using hydrogen ion implantation [50,51], a process which has similarities to the SmartCut TM SOI technique.…”

Section: Strain Relaxed-si 1−y Ge Y Virtual Substratesmentioning

confidence: 99%

Si/SiGe heterostructures: from material and physics to devices and circuits

Paul¹

2004

Semicond. Sci. Technol.

522

333

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Silicon germanium (SiGe) has moved from being a research material to accounting for a small but significant percentage of manufactured semiconductor devices. This percentage is predicted to increase substantially as SiGe begins to be used in complementary metal oxide semiconductor (CMOS) technology in the future to substantially improve performance. It is the development of Si/SiGe heterostructures which has enabled band structure and strain engineering allowing Si/SiGe to be used in many different ways to improve conventional microelectronic device performance along with allowing new concepts to be explored. This paper presents a review of the material properties, growth techniques, band structure and the main electronic devices of the Si/SiGe heterostructure system. In particular, the important device technologies in mainstream microelectronics of the SiGe heterostructure bipolar transistor (HBT) and strained-Si CMOS will be reviewed before future device and optoelectronics concepts are explored.

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“…One of the most exciting new techniques for virtual substrates was demonstrated using hydrogen ion implantation [50,51], a process which has similarities to the SmartCut TM SOI technique.…”

Section: Strain Relaxed-si 1−y Ge Y Virtual Substratesmentioning

confidence: 99%

Si/SiGe heterostructures: from material and physics to devices and circuits

Paul¹

2004

Semicond. Sci. Technol.

522

333

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“…Si 1Ϫx Ge x /Si heterostructures are also being considered for the raised source and drain structures in integrated circuits. [1][2][3] Due to its linewidth-independent low resistivity, low-temperature one-step annealing, and low silicon consumption, NiSi is one of the most promising candidates for contact to Si and SiGe layers. 4 Direct deposition of Ni and its alloys onto Si 1Ϫx Ge x in a self-aligned silicide process would be an efficient technique and would take the advantage of established technologies.…”

mentioning

confidence: 99%

Probing Ge Segregation in NiSi[sub 1−u]Ge[sub u] Using Micro-Raman Spectroscopy

Yao¹,

Tripathy²,

Z.³

2004

Electrochem. Solid-State Lett.

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The solid-state reaction of Ni on strained and relaxed ͑001͒ Si 0.8 Ge 0.2 has been studied by micro-Raman scattering with a particular emphasis on the influence of Ge-rich Si 1Ϫz Ge z segregation in NiSi 1Ϫu Ge u films. Raman scattering is found to be a sensitive and useful tool to probe such Ge-rich Si 1Ϫz Ge z segregation that takes place preferentially at the germanosilicide/Si 1Ϫx Ge x interface. From Raman measurements, the composition of Ge within Ge-rich Si 1Ϫz Ge z grains formed due to prolonged rapid thermal annealing can be mapped and the results show consistency with transmission electron microscopy. We have also observed that both shorter annealing time and addition of Pt can effectively suppress the Ge segregation at the interface. Furthermore, Raman scattering can clearly detect the onset temperature of Ge segregation for different thermal annealing conditions.

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“…Calculations show that for this approach to be effective, however, thicknesses will need to be reduced by an order of magnitude compared to what is currently typical (1-4 m). Some progress has been made in this area [9], but the threading dislocation densities in the thin buffer layers are currently too high for acceptable device operation.…”

Section: Discussionmentioning

confidence: 99%

Evidence of reduced self-heating in strained Si MOSFETs

Nicholas

Grasby

Parker

et al. 2005

IEEE Electron Device Lett.

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Pulsed measurements are used to investigate selfheating in strained-Si MOSFETs. From analysis of the data at elevated temperatures, the thermal resistances of the devices are extracted. These are found to be considerably lower than that obtained with a widely used theory. Thermal device simulations demonstrate that the discrepancy is due to an additional conduction path through the field oxide to overlapping aluminum contacts.

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High frequency n-type MODFETs on ultra-thin virtual SiGe substrates

Cited by 11 publications

References 8 publications

Si/SiGe heterostructures: from material and physics to devices and circuits

Si/SiGe heterostructures: from material and physics to devices and circuits

Probing Ge Segregation in NiSi[sub 1−u]Ge[sub u] Using Micro-Raman Spectroscopy

Evidence of reduced self-heating in strained Si MOSFETs

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