High-Frequency Characteristic Fluctuations of Nano-MOSFET Circuit Induced by Random Dopants

Li, Yiming; Hwang, C. S.

doi:10.1109/tmtt.2008.2007077

Cited by 42 publications

(21 citation statements)

References 46 publications

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“…The decrease in the aspect ratio of the device seems to improve dc characteristics; however, because of an increase in the threshold voltage and a decrease in the channel width, a device with a smaller aspect ratio may have a lower transconductance (g m ). To evaluate the impact of the variations of these dc characteristics on analog and digital circuits, the device transport equations are coupled with the circuit conservation equations and solved self-consistently to evaluate circuit performance [24][25][26]. Figure 2.…”

Section: Device Characteristicsmentioning

confidence: 99%

The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit

Hwang

2009

Semicond. Sci. Technol.

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The silicon (Si) surrounding-gate metal-oxide-semiconductor field-effect transistor (MOSFET) has ultimate gate structures and is a potential candidate for use in next-generation high-performance nano-devices. However, because of limitations of the fabrication process, theoretically ideally round shape of the surrounding gate may not always guarantee. These limitations may lead to the formation of an ellipse-shaped surrounding gate with major (a) and minor (b) axes of different lengths. In this study, the effect of the geometry aspect ratio, a/b, on the dc and ac characteristics of the 16 nm gate ellipse-shaped surrounding-gate MOSFETs and circuits is examined by using a three-dimensional coupled device-circuit simulation technique. The dependences of electrical characteristics on the geometry aspect ratio are evaluated with reference to various device characteristics and the circuit properties, including the circuit gain, the 3 dB bandwidth, the unity-gain bandwidth, the rise/fall time and the delay time. In analog circuits, the device with an aspect ratio of less than 1 is promising because the short-channel effect is suppressed. However, for a digital circuit configuration, the transient response of the circuit relies on the charge/discharge capability of the transistor. Thus, a device with a large aspect ratio, such as 2, will be more suitable for digital applications.

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Section: Device Characteristicsmentioning

confidence: 99%

The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit

Hwang

2009

Semicond. Sci. Technol.

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“…We can obtain the wide unity-gain bandwidth by T cap increasing and x decreasing. The unity-gain bandwidth is proportional to g m /C G , 43 and the variations of g m are relatively larger than C G under the conditions of different T cap and x. Therefore, g m dominates the influence of unity-gain bandwidth, and the result is corresponding to Fig.…”

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confidence: 93%

Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1−xGaxAs channel capping layer

Huang

2015

AIP Advances

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In this work, we study characteristics of 14-nm-gate InGaAs-based trigate MOSFET (metal-oxide-semiconductor field effect transistor) devices with a channel capping layer. The impacts of thickness and gallium (Ga) concentration of the channel capping layer on the device characteristic are firstly simulated and optimized by using three-dimensional quantum-mechanically corrected device simulation. Devices with In1−xGaxAs/In0.53Ga0.47As channels have the large driving current owing to small energy band gap and low alloy scattering at the channel surface. By simultaneously considering various physical and switching properties, a 4-nm-thick In0.68Ga0.32As channel capping layer can be adopted for advanced applications. Under the optimized channel parameters, we further examine the effects of channel fin angle and the work-function fluctuation (WKF) resulting from nano-sized metal grains of NiSi gate on the characteristic degradation and variability. To maintain the device characteristics and achieve the minimal variation induced by WKF, the physical findings of this study indicate a critical channel fin angle of 85o is needed for the device with an averaged grain size of NiSi below 4x4 nm2.

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“…In this work, experimentally validated three-dimensional (3D) quantum drift-diffusion device simulation [7,8,11,12] coupled with device-circuit simulation [12,13] is simultaneously conducted to explore the device and digital circuit characteristics of multi-fn transistors with different fin aspect ratios (AR = 2, 1, 0.5). The electrical characteristics of the devices are studied in terms of the threshold voltage (V th ) roll-off, driving current, transconductance, gate capacitance and intrinsic gate delay characteristics.…”

Section: Introductionmentioning

confidence: 99%

“…The very similar cross-section area and V th indicate having the same control volume of the device channel under the same operation condition. The device transport characteristics are then calculated by solving a set of 3D density-gradient equations coupled with Poisson equations as well as electron-hole current continuity equations [7,8,11,12] under our parallel computing system [14,15]. [12,13].…”

Section: Introductionmentioning

confidence: 99%

“…The device transport characteristics are then calculated by solving a set of 3D density-gradient equations coupled with Poisson equations as well as electron-hole current continuity equations [7,8,11,12] under our parallel computing system [14,15]. [12,13]. It is worth noting that the physical models adopted in the 3D quantum-mechanically corrected device equations were calibrated with the fabricated and measured samples for the best accuracy [8].…”

Section: Introductionmentioning

confidence: 99%

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Electrical characteristics dependence on the channel fin aspect ratio of multi-fin field effect transistors

Cheng

2009

Semicond. Sci. Technol.

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In this work we investigate the impact of the fin number and structure on device dc and dynamic behaviors of multi-fin field effect transistor (FET) circuits. Based on the same channel volume, multi-fin FETs with different fin aspect ratio (AR ≡ fin height/fin width) are explored using an experimentally validated three-dimensional device simulation. The multi-fin FinFET (AR = 2) has a better channel controllability than the tri-gate (AR = 1) and the quasi-planar (AR = 0.5) FETs. Besides, the 6T SRAM with triple-fin FinFETs provides the largest static noise margin because of the largest transconductance. Notably, though the FinFETs are with a large effective fin width and driving current, the larger gate capacitance may limit the intrinsic device gate delay. The transient characteristics of multi-fin inverters are further examined with different load capacitance (C load). As C load is increased, the impact of the device intrinsic gate capacitance on transient characteristcs is decreased and the delay time compared with that of single-fin inverters is smaller due to being dominated by the driving current of the transistor. Consequently, the multi-fin FinFET circuits exhibit a smallest delay time. The results of the study provide an insight into the dc and transient characteristics of multi-fin transistors and associated digital circuits.

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High-Frequency Characteristic Fluctuations of Nano-MOSFET Circuit Induced by Random Dopants

Cited by 42 publications

References 46 publications

The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit

The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit

Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1−xGaxAs channel capping layer

Electrical characteristics dependence on the channel fin aspect ratio of multi-fin field effect transistors

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