High energy N+ ion implantation in 4H–SiC

Oliviero, E.; Lazar, Mihai; Gardon, A.; Peaucelle, C.; Perrat, A.; Grob, J.J.; Raynaud, Christophe; Planson, Dominique

doi:10.1016/j.nimb.2007.01.256

Cited by 8 publications

(6 citation statements)

References 12 publications

(12 reference statements)

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“…Two of these samples (D = 5 × 10 14 , E = 180 keV) implanted at low and high temperatures are exemplarily annealed according to common annealing conditions resulting in high activation [16,25,26]. In order to avoid any out diffusion of the implanted dopants, the samples are covered with a carbon cap with an expected thickness of 500 nm.…”

Section: Methodsmentioning

confidence: 99%

Phosphorus implantation into 4H-SiC at room and elevated temperature

Müting

Bobal

Vines

et al. 2021

Semicond. Sci. Technol.

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Phosphorus implantation is essential to create localized n-type doped regions in 4H-SiC. The realized profiles may, however, deviate from the desired ones, affecting device properties. In order to characterize typical process parameters and to enable correct prediction of the desired structures, phosphorous implantation into 4H-SiC with a variety of doses and energies is performed at room and elevated temperature. Exemplary post-implantation annealing shows no significant influence on the phosphorus distribution. The as-implanted profiles, analyzed by secondary ion mass spectrometry, show a clear dependence on implantation dose and temperature. High sample temperature at implantation suppresses channeling in case of low and medium doses due to increased lattice vibrations, while crystal damage is restored in case of high doses leading to increased opportunities for channeling, pointing toward different crystal damage and energy loss mechanisms. Finally, the Monte Carlo profiles of the simulation tools stopping and range of ions in matter (SRIM) and Sentaurus Process are critically compared with the experimental profiles.

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Section: Methodsmentioning

confidence: 99%

Phosphorus implantation into 4H-SiC at room and elevated temperature

Müting

Bobal

Vines

et al. 2021

Semicond. Sci. Technol.

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“…Multiple energy implants always started with the highest energy. To electrically activate the Al and N ion implanted dopants, post-implantation annealing at 1700°C during 30 min has been performed in a RF-induction furnace with a C-cap [5]. [6].…”

Section: Methodsmentioning

confidence: 99%

The channeling effect of Al and N ion implantation in 4H–SiC during JFET integrated device processing

Lazar

Laariedh

Cremillieu

et al. 2015

Nuclear Instruments and Methods in Physics Research Section B:

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a b s t r a c tA strong channeling effect is observed for the ions of Al and N implanted in 4H-SiC due to its crystalline structure. This effect causes difficulties in subsequent accurate estimation of the depth of junctions formed by multiple ion implantation steps. A variety of lateral JFET transistors integrated on the same 4H-SiC wafer have been fabricated. Secondary Ion Mass Spectrometry measurements and Monte-Carlo simulations were performed in order to quantify and control the channeling effect of the implanted ions. A technological process was established enabling to obtain devices working with the presence of the channeling effect.

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“…The post-implantation annealing has been performed at 1700°C during 30 min in an RF-heated furnace. Prior to the annealing, the SiC surface has been protected with a C-cap formed by photoresist baking [6].…”

Section: Methodsmentioning

confidence: 99%

VLS Grown 4H-SiC Buried P<sup>+</sup> Layers for JFET Lateral Structures

Sejil

Laariedh

Lazar

et al. 2015

MSF

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Lateral JFET transistors have been fabricated with N and P-type channels tentatively integrated monolithically on the same SiC wafer. Buried P+SiC layers grown by Vapor-Liquid-Solid (VLS) selective epitaxy were utilized as source and drain for the P-JFET and as gate for the N-JFET. The ohmicity of the contacts, both on VLS grown P+and ion implanted N+layers, has been confirmed by Transfer Length Method (TLM) measurements. A premature leakage current is observed on the P/N junction created directly by the P+VLS gate layer, probably due to imperfect VLS (P+) / CVD (N+) SiC interface.

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High energy N+ ion implantation in 4H–SiC

Cited by 8 publications

References 12 publications

Phosphorus implantation into 4H-SiC at room and elevated temperature

Phosphorus implantation into 4H-SiC at room and elevated temperature

The channeling effect of Al and N ion implantation in 4H–SiC during JFET integrated device processing

VLS Grown 4H-SiC Buried P<sup>+</sup> Layers for JFET Lateral Structures

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