High Efficiency Hot Electron Injection for EEPROM Applications Using a Buried Injector

Hemink, G.; Wijburg, R.C.M.; Cuppens, R.; Middelhoek, J.

doi:10.7567/ssdm.1989.a-8-2

Cited by 4 publications

(4 citation statements)

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“…At the University of Twente a new way of programming an EEPROM, by means of hot electron injection, has been developed. This type of non-volatile memory is known as the VIPMOS EEPROM [9,10]. The acronym VIPMOS stands for vertical injection punchthrough based metal oxide semiconductor.…”

Section: Breakdown In Vipmos Eeprom Devicesmentioning

confidence: 99%

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Dielectric breakdown II: related projects at the University of twente

1997

Microelectronics Reliability

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In this paper an overview is given of the related activities in our group of the University of Twente. These are on thin film transistors with the irdaerent difficulty of making a gate dielectric at low temperature, on thin dielectrics for EEPROM devices with well-known requirements with respect to charge retention and endurance and, finally, on thin film diodes in displays with unexpected breakdown properties.

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Section: Breakdown In Vipmos Eeprom Devicesmentioning

confidence: 99%

“…During programming the gate dielectric is stressed. By means of applying the necessary voltages a punchthrough condition is created in which electrons become hot and are accelerated towards the floating gate [8,9]. A part of these electrons gain enough energy to surmount the potential barrier of the gate dielectric.…”

Section: Breakdown In Vipmos Eeprom Devicesmentioning

confidence: 99%

Dielectric breakdown II: related projects at the University of twente

1997

Microelectronics Reliability

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“…Besides, developing dielectric layers with proper electrical qualities becomes even more complex when, in addition to good isolating properties for low and moderate applied voltages, good conduction properties at high voltages are required. This concerns the vertical injection punchthrough based MOS (VIPMOS) EEPROM [4], [5]. During reading and programming (low and moderate voltages) charge leakage is unacceptable, while high voltages are needed for achieving interpoly tunneling as erasing mechanism [4], [5].…”

Section: Introductionmentioning

confidence: 99%

“…This concerns the vertical injection punchthrough based MOS (VIPMOS) EEPROM [4], [5]. During reading and programming (low and moderate voltages) charge leakage is unacceptable, while high voltages are needed for achieving interpoly tunneling as erasing mechanism [4], [5]. Because thermal oxidation of polycrystalline silicon leads to roughening of the silicon [6]- [16], thermally grown polyoxides exhibit a higher conductance and lower electric breakdown field than oxides on monocrystalline silicon, when the top electrode is positively biased.…”

Section: Introductionmentioning

confidence: 99%

Deposited inter-polysilicon dielectrics for nonvolatile memories

Klootwijk

Kranenburg

Woerlee

et al. 1999

IEEE Trans. Electron Devices

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Deposited instead of thermally grown oxides were studied to form very high-quality inter-polysilicon dielectric layers for embedded nonvolatile memory application. It was found that by optimizing the microstructure, i.e., texture and morphology of the polysilicon layers, and by optimizing the post dielectric deposition anneal, very high-quality dielectric layers can be obtained. In this paper it is shown on simple capacitor structure level and full EEPROM device level that the electrical properties of interpoly dielectric layers can be improved tremendously by using deposited dielectric layers with additional rapid thermal anneal. Typical results are: a high charge-to-breakdown (QBD 25 C/cm 2 ); low leakage currents and decreased charge trapping during constant current stress. An additional advantage is the low thermal budget, which is very attractive for embedded applications. However, results depend on the polysilicon preparation, dielectric type and RTP anneal environment.From electrical evaluation it appeared that even for deposited dielectric layers the influence of polysilicon surface roughness and corners is considerable.The optimized combination of flat polysilicon layers, deposited inter-polysilicon dielectric and additional optimized rapid thermal anneal have been applied in full EEPROM devices. Cycling over one million cycles was possible, which indicates an endurance improvement by a factor of 10.

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