High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation

Sung, Tze-Yun; Shieh, Yaw-Shih; Yu, Chun-Wang; Hsin, Hsi-Chin

doi:10.1109/pdcat.2006.70

Cited by 16 publications

(8 citation statements)

References 23 publications

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“…Thus, the 2-D IDCT computation using 1-D IDCT computation is as follows [1]. The proposed fast 1-D DCT processor According to (10), the proposed 1-D 8-point DCT processor is shown in Fig.…”

Section: -D Dct(x) = 1-d Dct((1-d Dct(x)) T ) (26)mentioning

confidence: 99%

“…The proposed fast 2-D DCT / IDCT processor Based on the proposed algorithm, the architecture of 2-D DCT(IDCT) can be implemented with two successive 1-D DCT(IDCT) processors and only one transpose memory [1][2][3]. The proposed architecture of 2-D DCT and IDCT is shown in Fig.…”

Section: Cmentioning

confidence: 99%

“…The conventional DCT architectures using distributed arithmetic involve complex hardware with high computation complexity [1][2][3][4][5][6][7][8][9][10]. The fast DCT architectures with low computation complexity are based on Loeffler proposed architecture using Flow-Graph Algorithm (FGA) [11][12][13].…”

mentioning

confidence: 99%

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A novel VLSI linear array for 2-D DCT/IDCT

Huang

Sung

Shieh

2010

2010 3rd International Congress on Image and Signal Processing

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This paper proposes an efficient one-dimensional (1-D) N-point discrete cosine and inverse discrete cosine transform (DCT/IDCT) architectures using sub-band decomposition algorithm. Based on the row-column decomposition technique, the two-dimensional (2-D) N×N DCT/IDCT architecture with two successive 1-D DCT/IDCT processors and one transpose memory is proposed. The orthonormal property of DCT/IDCT transformation matrices is fully used to simplify the hardware complexities. The proposed architectures with computation complexity O(5N/8) and O(3N/8) for DCT and IDCT, respectively, and low hardware complexity O(3N/8) for both DCT and IDCT are fully pipelined and scalable for variable-length 2-D DCT/IDCT computation.

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“…Thus, the 2-D IDCT computation using 1-D IDCT computation is as follows [1]. The proposed fast 1-D DCT processor According to (10), the proposed 1-D 8-point DCT processor is shown in Fig.…”

Section: -D Dct(x) = 1-d Dct((1-d Dct(x)) T ) (26)mentioning

confidence: 99%

Section: Cmentioning

confidence: 99%

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A novel VLSI linear array for 2-D DCT/IDCT

Huang

Sung

Shieh

2010

2010 3rd International Congress on Image and Signal Processing

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“…Clearly, the default IQDCIT cannot only reduce the arithmetic units but also further integrates the dequantization function. In [5], [6], besides adders for butterfly operations, additional full CORDIC processors need to count into the total required number for the 2-D transformation (80 shift-add for each pipelined CORDIC). Eventually, these CORDIC DCTs require much more shift-add operations than the proposed IQDCIT.…”

Section: Iii-b Variable Iteration Steps Of Cordicmentioning

confidence: 99%

“…Sung etc. implemented a VLSI design of CORDIC DCI/IDCT with five CORDIC processors [6], somehow H. Jeong etc. has also presented a similar method with six CORDIC processors [7].…”

Section: Introductionmentioning

confidence: 99%

A configurable IP core for inverse quantized discrete cosine and integer transforms with arbitrary accuracy

Sun

Zhang

Goetze

2010

2010 IEEE Asia Pacific Conference on Circuits and Systems

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An extended version of low-complexity IP Core for image/video transformations based on the CORDIC architecture is presented. This IP core is able to perform quantized 8×8 IDCT and quantized 8×8/4×4 H.264-inverse integer transforms on a configurable architecture by using only shift and add operations. Furthermore, the number for CORDIC iterations and compensation steps can be adjusted, which enables a trade-off between video compression quality in PSNR and computational complexity.

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