High Dynamic Range CMOS Imager Technologies for Biomedical Applications

Graf, H.-G.; Harendt, Christine; Engelhardt, Thorsten; Scherjon, Cor; Warkentin, Karsten; Richter, H.; Burghartz, Joachim N.

doi:10.1109/jssc.2008.2007437

Cited by 48 publications

(24 citation statements)

References 21 publications

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“…It is only important to mention that scaling limits of all light-absorbing devices are determined by the ability of photons to pass through small optical windows, and for a full transmission, the window size must be larger than the effective "size" of photon, which is on the order of wavelength l⋅ For visible light, this implies that the scaling limit of optical detectors is ∼1 mm. Currently, developments in micro-photosensors are supported by several emerging bioelectronic applications, such as retinal implants for artificial vision [51], "video pills" for visual inspection inside the human body [52], etc. For example, the image sensor demonstrated in [52] contains an array of light-sensitive pixels; the size of optical window of each pixel is about 2 mm.…”

Section: Optical Biosensorsmentioning

confidence: 99%

Sensors at the micro-scale

Zhirnov¹,

Cavin²

2015

Microsystems for Bioelectronics

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Section: Optical Biosensorsmentioning

confidence: 99%

Sensors at the micro-scale

Zhirnov¹,

Cavin²

2015

Microsystems for Bioelectronics

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“…9 shows the overall layout of the proposed CIS. The image sensor core area was 2 mm × 1.5 mm (3 mm 2 ) and the total chip size was 3 mm × 2.5 mm (7.5 mm 2 ).…”

Section: Power Reduction Techniques In the Active Modementioning

confidence: 99%

“…Visual information systems such as digital cameras, broadcast equipment, barcode readers, medical devices, and mobile appliances [1][2][3][4] are widely used in many industries. Also, the market for products based on visual information is rapidly growing.…”

Section: Introductionmentioning

confidence: 99%

Design of a 25 mW 16 frame/s 10-bit Low Power CMOS Image Sensor for Mobile Appliances

Kim¹,

Song²

2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flipflop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 µm CMOS process, the chip satisfies QVGA resolution (320 × 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

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“…To overcome these problems, several on-chip techniques have been proposed that can extend the dynamic range of image sensors. Several approaches have been proposed to extend the dynamic range of an image sensor [2][3][4][5][6][7][8][9]. Logarithmic pixel can achieve a dynamic range above 100 dB.…”

Section: Introductionmentioning

confidence: 99%

Linear-Logarithmic CMOS Image Sensor with Reduced FPN Using Photogate and Cascode MOSFET

Bae

Choi

Kim

et al. 2017

Proceedings of Eurosensors 2017, Paris, France, 3–6 September 2017

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Abstract:We propose a linear-logarithmic CMOS image sensor with reduced fixed pattern noise (FPN). The proposed linear-logarithmic pixel based on a conventional 3-transistor active pixel sensor (APS) structure has additional circuits in which a photogate and a cascade MOSFET are integrated with the pixel structure in conjunction with the photodiode. To improve FPN, we applied the PMOSFET hard reset method as a reset transistor instead of NMOSFET reset normally used in APS. The proposed pixel has been designed and fabricated using 0.18-μm 1-poly 6-metal standard CMOS process. A 120 × 240 pixel array of test chip was divided into 2 different subsections with 60 × 240 sub-arrays, so that the proposed linear-logarithmic pixel with reduced FPN could be compared with the conventional linear-logarithmic pixel. We confirmed a reduction of pixel response variation which affected image quality.

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High Dynamic Range CMOS Imager Technologies for Biomedical Applications

Cited by 48 publications

References 21 publications

Sensors at the micro-scale

Sensors at the micro-scale

Design of a 25 mW 16 frame/s 10-bit Low Power CMOS Image Sensor for Mobile Appliances

Linear-Logarithmic CMOS Image Sensor with Reduced FPN Using Photogate and Cascode MOSFET

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