High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs

Abstract

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (VGS-VT) and the higher drain/source voltage VDS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.

Process Corresponding Implications Associated with a Conclusive Model-Fit Current-Voltage Characteristic Curves

“…However, the electrical performances, mainly manifested in current-versus-voltage characteristic curves (I-V curves), are thus put to be parameter-extracted in the model, which takes advantage of sophisticated equivalent circuits for academic and industrial uses. Nevertheless, the measured I-V curves are speculated to be also fitted by the "modified" conventional formula [13][14][15][16][17][18].…”