High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC

Chen, Nai-Chen; Chou, Pang-Yen; Graeb, Helmut

doi:10.23919/date.2017.7927277

Cited by 8 publications

(4 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The minimum MIM capacitor size allowed in this process is 16 fF, occupying an area of 4 µm by 4 µm, yielding a total capacitance of 1 pF. To address the issues of chip area and power consumption, a mortise-tenon MOM capacitor [25] with 6.4 fF unit capacitance is employed in this design. Despite the non-linearity arising from the mismatch in the CDAC not being mitigated by NTF, the 6-bit CDAC reduces the system's complexity compared to higher-resolution CDACs used in previous studies [17][18][19].…”

Section: The Hybrid Switching Procedures and Optimal Logicmentioning

confidence: 99%

“…Despite the non-linearity arising from the mismatch in the CDAC not being mitigated by NTF, the 6-bit CDAC reduces the system's complexity compared to higher-resolution CDACs used in previous studies [17][18][19]. An optimized common-centroid CDAC floorplan and routing approach [26] are employed to minimize the mismatch, resulting in a DNL and INL within the acceptable range of ±0.5 LSB [25] for equivalent 10-bit resolution.…”

Section: The Hybrid Switching Procedures and Optimal Logicmentioning

confidence: 99%

See 1 more Smart Citation

A 10.31 ENOB 3.125MHz BW fully passive 2nd-order noise-shaping SAR ADC for low cost IoT sensor networks

Shen

Zhu

Shi

et al. 2024

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a fully passive 2nd-order noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) designed specifically for low-power and low-cost Internet of Things (IoT) applications. By optimizing the coefficients, a substantial 24 dB in-band quantization noise suppression is achieved. To further reduce power consumption and the total unit capacitor count, a hybrid switching procedure and optimal logic are utilized. The measurement result shows that this design achieves an effective number of 10.31 bits over a 3.125 MHz signal bandwidth. At a power supply of 1.8 V, the power consumption is measured to be 728 𝜇W with a sampling rate of 50 MS/s. Fabricated in 180-nm CMOS technology, the ADC core occupies an area of 0.117 mm 2 . The Schrier figure-of-merit (FoM) of 160.13 dB is obtained.

show abstract

Section: The Hybrid Switching Procedures and Optimal Logicmentioning

confidence: 99%

Section: The Hybrid Switching Procedures and Optimal Logicmentioning

confidence: 99%

A 10.31 ENOB 3.125MHz BW fully passive 2nd-order noise-shaping SAR ADC for low cost IoT sensor networks

Shen

Zhu

Shi

et al. 2024

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…This value may be lower than the smallest capacitor available in the process design kits. One solution to this issue is to design specific MOM capacitors, which are smaller than those in process design kits [31]. In our design, we considered a segmented DAC scheme where the total number of capacitors in the DAC array was reduced.…”

Section: Issues With a High-resolution Capacitive Dacmentioning

confidence: 99%

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

Bontems

Dzahini

2023

Chips

View full text Add to dashboard Cite

This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on a set of trimming capacitors was applied alongside a dynamic element matching (DEM) procedure to control the inherent linearity issues caused by the process mismatch. The SAR ADC and each additional algorithm were modeled in MATLAB to show their efficiency. Finally, a simple methodology was developed to allow for the fast estimation of signal-to-noise ratios (SNRs) without any FFT calculation.

show abstract

“…In recent years, advancements in manufacturing processes have made SAR ADC a more desirable option for medium-to-high precision applications due to its OPA-less and highly digital architecture [1,2,3]. The resolution of a SAR ADC is directly affected by the value of the unit capacitor in CDAC, which must be sufficiently large to meet accuracy requirements [4,5]. Additionally, as resolution increases, the number of unit capacitors in the CDAC also increases, resulting in a longer establishment time for comparator input voltage during sampling and successive approximation (SA) processes.…”

Section: Introductionmentioning

confidence: 99%

A CJ-LMS hybrid calibration algorithm in SAR ADC

Zhang,

Pu,

et al. 2023

IEICE Electron. Express

View full text Add to dashboard Cite

In this paper, a Code-Jump (CJ) assisted Least Mean Square (LMS) calibration algorithm for high resolution successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. This hybird algorithm does not require any specific input signal and has no impact on the ADC overall gain error. The revised LMS iteration algorithm is used to improve the accuracy of the lowest bits (LSBs) capacitor in the capacitivedigital-to-analog converter (CDAC), and the calibrated LSBs segment is used as reference capacitor to complete CJ calibration scheme. According to the results of 2000 Monte Carlo simulations, compared to the precalibration results, the hybrid CJ-LMS calibration method significantly improves the mean value of SNDR, increasing from 58.2dB to 70.6dB, while simultaneously reducing the sigma of the SNDR distribution from 3.1 dB to 0.3 dB.

show abstract

High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC

Cited by 8 publications

References 10 publications

A 10.31 ENOB 3.125MHz BW fully passive 2nd-order noise-shaping SAR ADC for low cost IoT sensor networks

A 10.31 ENOB 3.125MHz BW fully passive 2nd-order noise-shaping SAR ADC for low cost IoT sensor networks

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

A CJ-LMS hybrid calibration algorithm in SAR ADC

Contact Info

Product

Resources

About