High DC-Gain Two-Stage OTA Using Positive Feedback and Split-Length Transistor Techniques

Nebhen, Jamel; Masmoudi, Mohamed; Rahajandraibe, Wenceslas; Aguir, Khalifa

doi:10.1007/978-3-030-36368-0_24

Cited by 3 publications

(4 citation statements)

References 26 publications

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“…The amplifier of the first integrator is based on two stages architecture, as described in Fig. 5 [30]. The two stages architecture are respectively a folded cascode and a common source amplifier.…”

Section: Amplifier Circuit Of the First Integratormentioning

confidence: 99%

“…The first mirror is composed of transistor set (M15, M17, M19, M21) and the second mirror is composed of transistor set (M16, M18, M20, M22). The proposed idea consists of creating a positive feedback loop between the two outputs V out+ and V out− of the amplifier to increase the amplifier DC gain with the same UGBW value [30]. In this context, the terminal V out+ is assigned to the transistor drain M16 and the terminal V out− is assigned to the transistor drain M15.…”

Section: Amplifier Circuit Of the First Integratormentioning

confidence: 99%

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A Chopper Negative-R Delta-Sigma ADC for Audio MEMS Sensors

Nebhen¹,

Ferreira²

2022

Computer Modeling in Engineering &Amp; Sciences

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This paper presents a proposed low-noise and high-sensitivity Internet of Thing (IoT) system based on an M&NEMS microphone. The IoT device consists of an M&NEMS resistive accelerometer associated with an electronic readout circuit, which is a silicon nanowire and a Continuous-Time (CT)ADC. The first integrator of the ADC is based on a positive feedback DC-gain enhancement two-stage amplifier due to its high linearity and low-noise operations. To mitigate both the offset and 1/f noise, a suggested delay-time chopper negative-R stabilization technique is applied around the first integrator. A 65-nm CMOS process implements the CT ADC. The supply voltage of the CMOS circuit is 1.2-V while 0.96-mW is the power consumption and 0.1-mm 2 is the silicon area. The M&NEMS microphone and ADC complete circuit are fabricated and measured. Over a working frequency bandwidth of 20-kHz, the measurement results of the proposed IoT system reach a signal to noise ratio (SNR) of 102.8-dB. Moreover, it has a measured dynamic range (DR) of 108-dB and a measured signal to noise and distortion ratio (SNDR) of 101.3-dB.

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Section: Amplifier Circuit Of the First Integratormentioning

confidence: 99%

Section: Amplifier Circuit Of the First Integratormentioning

confidence: 99%

A Chopper Negative-R Delta-Sigma ADC for Audio MEMS Sensors

Nebhen¹,

Ferreira²

2022

Computer Modeling in Engineering &Amp; Sciences

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“…A desired gain-bandwidth (GBW) and a load capacitance (CL) are considered to evaluate the amplifier power consumption. If all amplifier transistors have the same overdrive voltage V = V − V , and if the output non-dominant pole is at least three times of the GBW, then the current consumption Itwo-stage of the two-stage operational transconductance amplifier (OTA) can be written as [29,30]. From Equation 10, it is clear that the maximum of the current is used to drive the compensation capacitors.…”

Section: Cmos Amplifier Implementationmentioning

confidence: 99%

“…The first stage is a differential OTA providing high gain, while the second stage is configured as a simple common-source stage to give maximum output swing. In contrast to cascode opamps, this topology isolates the gain and output swing requirements [29,30]. The DC-gain Ad and GBW expressions of the amplifier is given as ( ) ( ) where gm1 and gm3 denote the transconductance of transistor M1 and M3, r01, r02, r03, and r011 denote the output resistance of transistors M1, M2, M3, and M11, respectively.…”

Section: Cmos Amplifier Implementationmentioning

confidence: 99%

A 5-nV/√Hz Chopper Negative-R Stabilization Preamplifier for Audio Applications

2020

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This paper presents a low-noise and low-power audio preamplifier. The proposed low-noise preamplifier employs a delay-time chopper stabilization (CHS) technique and a negative-R circuit, both in the auxiliary amplifier to cancel the non-idealities of the main amplifier. The proposed technique makes it possible to mitigate the preamplifier 1/f noise and thermal noise and improve its linearity. The low-noise preamplifier is implemented in 65 nm complementary metal-oxide semiconductor (CMOS) technology. The supply voltage is 1.2 V, while the power consumption is 159 µW, and the core area is 192 µm2. The proposed circuit of the preamplifier was fabricated and measured. From the measurement results over a signal bandwidth of 20 kHz, it achieves a signal-to-noise ratio (SNR) of 80 dB, an equivalent-input referred noise of 5 nV/√Hz and a noise efficiency factor (NEF) of 1.9 within the frequency range from 1 Hz to 20 kHz.

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