High data rate and flexible hardware QC-LDPC decoder for satellite optical communications

Pignoly, Vincent; Gal, Bertrand Le; Jégo, Christophe; Gadat, Benjamin

doi:10.1109/istc.2018.8625274

Cited by 10 publications

(6 citation statements)

References 16 publications

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“…Indeed, FG LDPC codes enables decoder throughput that has not been yet obtained to the best of our knowledge for DVB-S2 codes. Very promising results are presented in [20] in which it is shown that a 10.6 Gbps decoder can be implemented into a Zynq xczu9e FPGA. End-to-end simulations have shown the feasibility of quasi-error free communication link for both scenario with FEC code rate of 4/5 and interleaver duration around 10 ms.…”

Section: Resultsmentioning

confidence: 99%

Forward error correcting code for high data rate LEO satellite optical downlinks

Poulenard

Gadat

Chouteau

et al. 2019

International Conference on Space Optics — ICSO 2018

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A simulation framework based on a physical-layer based abstraction to predict physical layer performances and to compare different forward error correcting (FEC) codes is presented. This framework is used to jointly design interleaving and FEC schemes for free space optical link. A sub-class of regular Low-Density Parity-Check codes is shown to be an interesting alternative to current space communication standard for optical links that require low error floor and high decoder throughput. End-to-end simulations show the feasibility of error free link from a LEO satellite to a high complexity ground station at 25Gbits/s and from a LEO satellite to low complexity optical ground station at 10 Gbits/s. The proposed protection scheme is composed of FG LDPC code and a bit interleaver to span the burst of errors.

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Section: Resultsmentioning

confidence: 99%

Forward error correcting code for high data rate LEO satellite optical downlinks

Poulenard

Gadat

Chouteau

et al. 2019

International Conference on Space Optics — ICSO 2018

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“…In comparison to the designs presented in [18], [19], our architecture, even with a single decoder, achieves a throughput of more than two times while maintaining a similar level of resource consumption. In [22], the proposed decoder is based on an ASIP architecture, which leads to reduced hardware complexity and enhanced decoding throughput. However, it's noteworthy that the decoder in [22] consumes a significant amount of LUTs, while FF resources are relatively low.…”

Section: Fpga Implementation and Analysismentioning

confidence: 99%

“…In [22], the proposed decoder is based on an ASIP architecture, which leads to reduced hardware complexity and enhanced decoding throughput. However, it's noteworthy that the decoder in [22] consumes a significant amount of LUTs, while FF resources are relatively low. In the realm of hardware design, a well-balanced allocation of resources contributes to achieving shorter critical path delays, and this point is further validated by the comparison of implementation results.…”

Section: Fpga Implementation and Analysismentioning

confidence: 99%

“…In the realm of hardware design, a well-balanced allocation of resources contributes to achieving shorter critical path delays, and this point is further validated by the comparison of implementation results. In [22], the critical path limits the FPGA frequency up to 260 MHz. In contrast, the utilization of both LUTs and FFs resources of our proposed decoder is more balanced, resulting in a shorter critical path delay and the potential for higher decoding throughput.…”

Section: Fpga Implementation and Analysismentioning

confidence: 99%

“…However, new laser communications in space expect higher throughput and there comes the need of innovative methods to reach more than 10 Gb/s [22]. Very promising results are presented in [22] in which it is shown that a 10.6 Gb/s decoder can be implemented based on an Application Specific Instruction Set (ASIP) architecture. However, this high hardware efficiency comes at the cost of reduced programmability.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Universal High-Throughput and Low-Complexity LDPC Decoder for Laser Communications

Kang,

An,

Zhu

2024

IEEE Access

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To address the challenges posed by propagation channel impairments and to meet the high data rate requirements of laser communications, this study introduces a pioneering low-density parity-check (LDPC) decoder characterized by its high throughput and low complexity. The unique design of this decoder, based on an inter-frame pipeline and intra-frame parallel (IFPP-IFP) scheme, is specifically tailored to maximize the efficiency of processing units, leading to a substantial increase in decoding throughput. The implementation of IFPP is realized through a novel full-overlap message passing (FOMP) scheme and a dynamic address access (DAA) algorithm, distinguishing it from current solutions. Additionally, the decoder employs a message packing strategy and low-complexity data alignment units to effectively achieve IFP. Compared to existing solutions, our hardware implementation on the Xilinx XCKU060 FPGA demonstrates significant progress. The decoder achieves a decoding throughput of 2.67 Gb/s at 10 iterations and 350MHz. Remarkably, when five decoders are used on a single FPGA device, the throughput soars to 13.3 Gb/s, outperforming state-of-the-art designs by 1.3 times and concurrently reducing resource consumption by half. This combination of resource efficiency and enhanced throughput highlights the innovative and superior nature of our proposed approach.

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High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices

Gal

Pignoly

Jégo

2022

Design and Architecture for Signal and Image Processing

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High data rate and flexible hardware QC-LDPC decoder for satellite optical communications

Cited by 10 publications

References 16 publications

Forward error correcting code for high data rate LEO satellite optical downlinks

Forward error correcting code for high data rate LEO satellite optical downlinks

Universal High-Throughput and Low-Complexity LDPC Decoder for Laser Communications

High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices

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