High conductance Ge p-channel heterostructures realized by hybrid epitaxial growth

Abstract

Strained Ge p-channel heterostructures have been realized by hybrid-epitaxial growth. Strain-tuning Si 0.4 Ge 0.6 virtual substrates were grown by ultra-high vacuum chemical vapour deposition and active layers were deposited by solid-source molecular beam epitaxy at low temperature. Following ex situ annealing, Hall effect measurements revealed a hole mobility of 1900 cm 2 V −1 s −1 at 300 K (27 000 cm 2 V −1 s −1 at 10 K), with a density of 1.8 × 10 12 cm −2 , giving a conductance in excess of current Ge heterostructures. Using a maximum-entropy mobility-spectrum analysis, 1.0 × 10 12 cm −2 of these holes were found to have a mobility of 2700 cm 2 V −1 s −1 at 300 K.

New RP‐CVD grown ultra‐high performance selectively B‐doped pure‐Ge 20 nm QWs on (100)Si as basis material for post‐Si CMOS technology

“…Two designs of modulation doped heterostructure grown by reduced pressure chemical vapour deposition (RP-CVD) were used and included a normal structure (doping above the Ge channel and inverted structure (doping beneath the Ge channel). The mobility (μ H ) for the normal structure was measured to be 1.34×10 6 cm 2 /Vs with a sheet density (p s ) of 2.9×10 11 cm -2 at 1.5 K, and μ H = 3970 cm 2 /Vs and p s ~1×10 11 cm -2 for room temperature, determined from simulation using the Maximum Entropy-Mobility Spectrum Analysis (ME-MSA) method.…”

Ultra high hole mobilities in a pure strained Ge quantum well

“…Both low temperature (LT) [1][2][3][4][5] and room temperature (RT) [6][7][8][9][10][11][12][13][14][15] measurements have been studied in order to obtain a better understanding of the fundamental physics behind these transport properties. It is found that to obtain an improved electrical performance for sGe, a high purity Ge QW needs to be grown on a Ge-rich buffer layer with a low defect density.…”

Si1-xGex/Si Interface Profiles Measured to Sub-Nanometer Precision Using uleSIMS Energy Sequencing

“…Additional tailoring is, however, possible through varying the layer thickness, composition, and dopant. Critical to the device functionality and its subsequent exploitation is the quality of the buried interfaces because these can influence the overall performance [1]. To meet the semiconductor technology roadmap [2], heterostructures have continually decreased in size with concomitant increases in their complexity.…”