High concentration effects of neutral-potential-well interface traps on recombination dc current-voltage lineshape in metal-oxide-silicon transistors

Chen, Zuhui; Jie, B.B.; Sah, C. T.

doi:10.1063/1.2993916

Cited by 4 publications

(2 citation statements)

References 14 publications

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“…For a three-dimensional bulk model, the ratio of neutral electron traps to neutral hole traps is given by 19…”

Section: Theory Of R-dciv Methodsmentioning

confidence: 99%

Effects of Transitional Layer of Gate Insulator on Recombination DC Current–Voltage Lineshape in Metal–Oxide–Semiconductor Transistors

Chen¹,

Zhou²,

Zhu³

2009

Jpn. J. Appl. Phys.

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Industry is seeking for new materials and technologies to replace SiO 2 in order to suppress leakage current, improve device performance, and keep scaling without major changes in the fabrication process. The major problem of high-k dielectric implementation is the fabrication challenge to integrate high-k materials into the manufacturing processes. In this paper, the effects of transitional layer of high-k gate insulator on the electron-hole recombination direct-current current-voltage (R-DCIV) properties are theoretically analyzed using the steady-state Shockley-Read-Hall kinetics. It shows that the gate transitional layer has negligible effect on the R-DCIV lineshape due to the small change of gate capacitance induced by the transitional layer. The transitional layer of gate insulator could offer an alternative way for industry to implement high-k dielectric since the transitional layer can alleviate the fabrication challenge in the manufacturing processes of modern very-large-scale integration (VLSI) technology.

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“…For a three-dimensional bulk model, the ratio of neutral electron traps to neutral hole traps is given by 19…”

Section: Theory Of R-dciv Methodsmentioning

confidence: 99%

Effects of Transitional Layer of Gate Insulator on Recombination DC Current–Voltage Lineshape in Metal–Oxide–Semiconductor Transistors

Chen¹,

Zhou²,

Zhu³

2009

Jpn. J. Appl. Phys.

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“…When an appropriate voltage is applied to the back gate, the back channel will be depleted totally and the electrons and holes near the interface traps at the back interface will be adequate. The recombination rate of interface traps will reach the maximum and the density of interface traps will be calculated according to the SRH recombination theory [19][20][21]. In this paper, based on the DCIV method, the radiation characteristics of SOI NMOSFETs with different process conditions are investigated.…”

Section: Introductionmentioning

confidence: 99%

Applications of Direct-Current Current–Voltage Method to Total Ionizing Dose Radiation Characterization in SOI NMOSFETs with Different Process Conditions

Zeng

et al. 2021

Electronics

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As a promising candidate in space radiation hardened applications, silicon-on-insulator (SOI) devices face the severe problem of total ionizing dose (TID) radiation because of the thick buried oxide (BOX) layer. The direct-current current–voltage (DCIV) method was applied for studying TID radiation of SOI metal–oxide–semiconductor field–effect transistors (MOSFETs) with different manufacture processes. It is found that the peak of high-voltage well (PX) devices shows a larger left-shift and a slower multitude increase along with radiation dose, compared with that of low-voltage well (PV) devices. It is illustrated that the high P-type impurity concentration near back interface makes it more difficult to break up silicon hydrogen bonds, which gives the PX devices superiority in resisting the build-up of interface traps. The study results indicate that increasing doping concentration of the body region near the back-gate interface might be an alternative radiation hardening technique of SOI MOSFET devices to avoid the parasitic back transistors’ leakage.

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Surface recombination/generation velocity in metal-oxide-silicon field-effect transistors

Chen

Zhou

Zhu

et al. 2009

2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)

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High concentration effects of neutral-potential-well interface traps on recombination dc current-voltage lineshape in metal-oxide-silicon transistors

Cited by 4 publications

References 14 publications

Effects of Transitional Layer of Gate Insulator on Recombination DC Current–Voltage Lineshape in Metal–Oxide–Semiconductor Transistors

Effects of Transitional Layer of Gate Insulator on Recombination DC Current–Voltage Lineshape in Metal–Oxide–Semiconductor Transistors

Applications of Direct-Current Current–Voltage Method to Total Ionizing Dose Radiation Characterization in SOI NMOSFETs with Different Process Conditions

Surface recombination/generation velocity in metal-oxide-silicon field-effect transistors

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