High-Capacitance-Density ${p}$ -GaN Gate Capacitors for High-Frequency Power Integration

Tang, Gaofei; Kwan, M.-H.; Su, R.Y.; Yao, F.-W.; Lin, Yo-Sheng; Yu, Jingshu; Yang, Tao; Chern, C. H.; Tsai, Tom; Tuan, H.C.; Kalnitsky, Alexander; Chen, Kevin J.

doi:10.1109/led.2018.2854407

Cited by 29 publications

(8 citation statements)

References 18 publications

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“…For C g measurement, the drain electrode is connected to the source electrode, the gate‐biased voltage is swept from 0 to 6 V; for C iss , C oss , and C rss measurements, the gate‐biased voltage is 0 V and the V ds is swept from 0 to 300 V. Obvious decrease of C g at high temperatures can be observed; however, the C iss , C oss , and C rss show neglected changes at high temperatures. From [19], the measured C g can be lower than the intrinsic value when the channel resistance ( R CH ) increases at high temperatures due to the distribution effect, seen in (6). In this way, the measured variations cannot indicate the change of the intrinsic gate capacitance, meaning that the decrease of µ eff induces larger error to the results when characterising C g .…”

Section: Resultsmentioning

confidence: 99%

High‐temperature electrical performances and physics‐based analysis of p‐GaN HEMT device

Liu

Tian

et al. 2020

IET Power Electronics

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High-temperature electrical performances of enhancement-mode (E-mode) high electron mobility transistor with ptype Gallium Nitride (GaN) gate cap are evaluated here. The physics-based mechanisms behind the behaviours are also analysed by the simulations and analytical models. For static electrical performances, the changes of GaN bandgap and the interface states or traps are considered to be influential factors for the little variations of threshold voltage (V T). Meanwhile, the on-state resistance increases and trans-conductance decreases at high temperatures due to the reduction in electron mobility (µ eff). As for blocking characteristic, high temperature-induced increase of leakage current may result from multi-reasons, such as the increase of intrinsic carrier concentration and lowering of trap barrier. In addition, a segmental method is presented to understand the gate leakage current at high temperatures. For capacitance characteristics, the increase of channel resistance makes the measured gate capacitance lower than the intrinsic value. For dynamic electrical performances, the high temperature-induced decrease of µ eff leads to the increase of plateau voltage, bringing the decreases of total switching time and total switching energy loss, which are quite different from those of the devices with traditional metal-oxide-semiconductor structures.

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Section: Resultsmentioning

confidence: 99%

High‐temperature electrical performances and physics‐based analysis of p‐GaN HEMT device

Liu

Tian

et al. 2020

IET Power Electronics

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“…Schematic 3D illustration of the metallization for source, gate and drain with (a) comb structure, (b) matrix structure and (c) measured output characteristic for e-mode power transistors with the same chip area of 2×2 mm 2 and different layouts. [44]. Another way is to use the gate structure (metal/p-GaN/AlGaN/GaN) as a capacitor to provide a high capacitance density.…”

Section: B Passive Componentsmentioning

confidence: 99%

“…Another way is to use the gate structure (metal/p-GaN/AlGaN/GaN) as a capacitor to provide a high capacitance density. The explanation and modeling of the capacitance is described in [44] using the energy band diagram. However, the performance can be affected by increased leakage currents, threshold voltage instability and gate-stress degradation.…”

Section: B Passive Componentsmentioning

confidence: 99%

Building Blocks for GaN Power Integration

Basler¹,

Reiner

Moench

et al. 2021

IEEE Access

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GaN technology is on the advance for the use in power ICs thanks to space-saving integrated circuit components and the increasing number of integrated devices. This work experimentally investigates a number of key building blocks for GaN power integration. First, an overview of the active and passives devices of the technology is given with focus on area-efficient layouts for power transistors and limitations of on-chip capacitors and inductors with comparison to other IC technologies. Digital and analog basic circuits as part of device libraries are examined and optimized with regard to area-efficiency. The NOT gates have active areas as low as 56.7 µm 2 and max. static currents of 0.12 mA with high noise margins. Further digital gates are presented. For the analog circuits, differential amplifiers and voltage reference concepts are presented and compared. Finally, GaN power integration is discussed, and integration levels are defined and described. The GaN technology is compared with other IC technologies, and future challenges and perspectives are shown. GaN power integration based on building blocks aims to exploit the full potential of the lateral GaN technology in order to compete with Si-based IC technologies in the future.INDEX TERMS Gallium nitride, integrated circuit technology, power integrated circuits, logic circuits, analog circuits

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“…Efficient power switches usually require a positive VTH that is sufficiently large, along with low RON,SP and high VBR [2], which is however very challenging in GaN MOSHEMTs. Among several reported techniques, such as fluorine plasma treatment [3]- [5] and p-GaN gate [6]- [8], recessing the barrier under the gate region [9]- [12], either partially or fully, can lead to large VTH [13], which however typically degrades RON. While reducing the gate recess length can improve RON, it also results in a negative shift of VTH [14].…”

Section: Device Design and Fabricationmentioning

confidence: 99%

High-Voltage Normally-off Recessed Tri-Gate GaN Power MOSFETs With Low on-Resistance

Zhu

Nela

et al. 2019

IEEE Electron Device Lett.

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In this letter, we present normally-off GaN-on-Si MOSFETs based on the combination of tri-gate with a short barrier recess to yield a large positive threshold voltage (VTH), while maintaining a low specific on resistance (RON,SP) and high current density (I D). The tri-gate structure offered excellent channel control, enhancing the VTH from +0.3 V for the recessed to +1.4 V for the recessed tri-gate, along with a much reduced hysteresis in VTH, and a significantly increased transconductance (gm). Additional conduction channels at the sidewalls of the tri-gate trenches compensated the degradation in ON resistance (RON) from the gate recess, resulting in a small RON of 7.32 ± 0.26 Ω•mm for LGD of 15 μm, and an increase in the maximum output current (I D max). In addition, the tri-gate inherently integrates a gateconnected field-plate (FP), which improved the breakdown voltage (VBR) and reduced the degradation in dynamic RON. With proper passivation techniques, these devices could be very promising as high performance power switches for future power applications.

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High-Capacitance-Density ${p}$ -GaN Gate Capacitors for High-Frequency Power Integration

Cited by 29 publications

References 18 publications

High‐temperature electrical performances and physics‐based analysis of p‐GaN HEMT device

High‐temperature electrical performances and physics‐based analysis of p‐GaN HEMT device

Building Blocks for GaN Power Integration

High-Voltage Normally-off Recessed Tri-Gate GaN Power MOSFETs With Low on-Resistance

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