High bandwidth application on 2.5D IC silicon interposer

Wang, Chen-Chao; Cheng, Hung-Hsiang; Chung, Ming-Feng; Pan, Po-Chih; Ho, Ching-Yen; Chiu, Chi-Tsung; Hung, Chih-Pin

doi:10.1109/isaf.2014.6917929

Cited by 1 publication

(1 citation statement)

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“…A data plane component is located outside the switching ASIC, but on the same chassis. They are connected through either a custom high bandwidth interconnect technology (e.g., 2.5D silicon interposer [63]) or existing technology such as PCIe. This option could achieve lower performance than the above option, but provide higher extensibility by allowing for plugging in new components.…”

Section: Switch-external Data Plane Integrationmentioning

confidence: 99%

A Roadmap for Enabling a Future-Proof In-Network Computing Data Plane Ecosystem

Kim¹,

Lazarev²,

Tracy³

et al. 2021

Preprint

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As the vision of in-network computing becomes more mature, we see two parallel evolutionary trends. First, we see the evolution of richer, more demanding applications that require capabilities beyond programmable switching ASICs. Second, we see the evolution of diverse data plane technologies with many other future capabilities on the horizon. While some point solutions exist to tackle the intersection of these trends, we see several ecosystem-level disconnects today; e.g., the need to refactor applications for new data planes, lack of systematic guidelines to inform the development of future data plane capabilities, and lack of holistic runtime frameworks for network operators. In this paper, we use simple-yet-instructive emerging application-data plane combination to highlight these disconnects. Drawing on these lessons, we sketch a high-level roadmap and guidelines for the community to tackle these to create a more thriving "future-proof" data plane ecosystem.

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Section: Switch-external Data Plane Integrationmentioning

confidence: 99%