High‐accuracy MOS A/D converter with inherent self‐compensation

Abstract

Considerable effort has recently been devoted to the development of monolithic, integrated‐circuit (IC) analog‐to‐digital (A/D) converters. However, the accuracy of successive‐approximation A/D converters has been limited to 10 bits due to the linewidth variations in the state‐of‐the‐art IC processing. Higher accuracies up to 12 bits have been realized only by trimming passive elements. In this paper, an A/D converter with an inherent (on‐chip) “self‐compensation” circuit is proposed which enables high‐accuracy analog‐to‐digital conversion without trimming. the principle and circuit construction of the new A/D converter are described. Fabrication and characterization of an experimental device are also discussed. The circuit described is a successive‐approximation MOS A/D converter, in which the input charge stored on a capacitor array is redistributed over the capacitors. the errors in the capacitances are evaluated prior to the conversion step using the array itself as a reference. the correction charge is generated automatically during the redistribution step, referring to the correction data. Charge correction is done simply by applying an appropriate voltage to a correction capacitor which is added to the array. This simple circuit is easy to build using a monolithic IC technology. A 3 μm CMOS IC technology was used to fabricate experimental circuits to build a 14‐bit A/D converter. Performance evaluation of the circuits demonstrates that the method proposed here has reduced the linearity error by 3 bits from 8 LSBs to 1 LSB.