High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications

Wang, Jiun-Ping; Kuang, Shiann-Rong; Liang, Shish-Chang

doi:10.1109/tvlsi.2009.2032289

Cited by 114 publications

(83 citation statements)

References 20 publications

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“…Finally, the approximate multipliers are applied to the design of a low-pass FIR filter and they show better performance than other approximate Booth multipliers. Jiun-Ping Wang et al [3] This paper presents the design of high-accuracy fixed-width modified Booth multipliers. To reduce the truncation error, firstly slightly modify the partial product matrix of Booth multiplication and then derive an effective error compensation function that makes the error distribution be more symmetric to and centralized in the error equal to zero, leading the fixed-width modified Booth multiplier to very small mean and mean-square errors.In addition, a simple compensation circuit mainly composed of the simplified sorting network is also proposed.…”

Section: Honglan Jiang Et Al [2]mentioning

confidence: 99%

A Review of Different Methods for Booth Multiplier

Kalia¹,

Mittal²

2017

IJERA

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In this review paper, different type of implementation of Booth multiplier has been studied. Multipliers has great importance in digital signal processor, so designing a high-speed multiplier is the need of the hour. Advantages of using modified booth multiplier algorithm is that the number of partial product is reduced. Different types of addition algorithms are also discussed which are used for addition operation of multiplier.Keyword -booth multiplier, modified booth multiplier, radix-8, fixed-width.

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Section: Honglan Jiang Et Al [2]mentioning

confidence: 99%

A Review of Different Methods for Booth Multiplier

Kalia¹,

Mittal²

2017

IJERA

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“…A self-compensation approach [3] using conditional mean method is presented to reduce the hardware complexity. In [4] and [5], by taking more information provided by Booth encoder, the compensation bias can reduce the truncation error with the huge area penalty. Besides, Song et al present binary threshold and more partial products for error compensation bias to reduce truncation error [6], and the hardware cost is increased, too.…”

Section: Introductionmentioning

confidence: 99%

A Comparison of Different Fixed Width Multipliers Based On MLCP

2015

IJSR

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Abstract:The fixed-width multiplier is attractive to many multimedia and digital signalprocessing systems which are desirable to maintain a fixed format and allow a little accuracy loss to output data. This brief includes a comparative study of different fixed-width Booth multipliers-PT(most accurate fixed width multiplier) and DT(least area requirement) fixed width multipliers with the Proposed accuracy-adjustment fixed-width Booth multipliers that compensates the truncation error using a multilevel conditional probability (MLCP) estimator.To consider the trade-off between accuracy and area cost, the MLCPprovides varying column information to adjust the accuracy with respect to system requirements. Unlike previous conditional-probability methods, the proposed MLCP uses entire nonzero code, namely MLCP, to estimate the truncation error and achieve higher accuracy levels. And a comparative study of different fixed width multipliers based on MLCP using differentfast adders such as carry look ahead adder, Kogge-stone adder etc are also included. The design was modeled using Verilog, simulated and synthesized using Xilinx ISE 14.7.

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“…Optimizing multiplier has attracted strong attention from researchers over the time. There are many implementation techniques that have been proposed such as Booth encoder [1], Wallace tree adder [2], Dadda tree adder [3], Cary-save adder [4], array multiplier [5], Modified Booth Encoder [6], etc. Generally, a multiplier implementation can be divided into three steps as can be seen in Fig.…”

Section: Introductionmentioning

confidence: 99%

A high-speed unsigned 32-bit multiplier based on booth-encoder and wallace-tree modifications

Luu

Hoang

Bui

et al. 2014

2014 International Conference on Advanced Technologies for Communications (ATC 2014)

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The delay of the multiplier plays a critical role in many high-speed implementations and processors such as RISC, DSP, and image processing cores, etc. In this paper, a design of unsigned 32-bit multiplier is proposed, aiming to achieve the best timing performance with an appropriate area. The proposed architecture consists of a modified Radix-4 Booth encoder, a modified Wallace Tree adder, and a Carry Look Ahead adder. The design has been verified successfully on DE2-115 and then synthesized to ASIC implementation. The FPGAbased experimental result shows that it has the resources of 1788 ALUTs. The synthesized result occupies an area of 58.28 mm 2 with 4.13 ns total delay (i.e. 242.13MHz maximum frequency).

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High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications

Cited by 114 publications

References 20 publications

A Review of Different Methods for Booth Multiplier

A Review of Different Methods for Booth Multiplier

A Comparison of Different Fixed Width Multipliers Based On MLCP

A high-speed unsigned 32-bit multiplier based on booth-encoder and wallace-tree modifications

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