HIFSuite: Tools for HDL Code Conversion and Manipulation

Bombieri, Nicola; Guglielmo, Giuseppe Di; Ferrari, Michele; Fummi, Franco; Pravadelli, Graziano; Stefanni, Francesco; Venturelli, Alessandro

doi:10.1155/2010/436328

Cited by 43 publications

(25 citation statements)

References 4 publications

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“…Heterogeneous Intermediate Format (HIF) [4] is a HW/SW description language structured as XML tree of classes. Each class describes a specific component or functionality that is typically provided by Hardware Description Languages (HDL) like VHDL, Verilog, and SystemC.…”

Section: Hifmentioning

confidence: 99%

“…Each message (3,4) represents either a message transfer or the corresponding reply. Transfers can be either synchronous (3) or asynchronous (4). Execution specification (5) represents the execution of a unit of behavior or action within the lifeline.…”

Section: Model and Constraint Specificationsmentioning

confidence: 99%

“…The RF module receives a sequence of bits from SPI with at least 0.33 µs between them (3) and then it collects bits into bytes and bytes into frames to be sent over the network with a blocking transfer. Therefore, RF sends frames to the network and the max duration of data transfer is constrained to 3.328 ms (4). The duration between sending data by the RF module and the complete handling of the reply is constrained to a maximum time of 4 µs (5).…”

Section: Systemc/tlm Code Generation Of Wsn Application (Case Study #1)mentioning

confidence: 99%

“…The RF module receives a sequence of bits from SPI with at least 33 µs between them (3). In addition, jitter constraint is also attached to the RF unit limiting the deviation of bit arrival time to a value ≤10 µs (4). VHDL code has been generated from UML sequence diagram which describes the interactions between application components.…”

Section: Figmentioning

confidence: 99%

See 3 more Smart Citations

HDL code generation from UML/MARTE sequence diagrams for verification and synthesis

Ebeid

Fummi

Quaglia

2015

Des Autom Embed Syst

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Design of Embedded Systems is becoming more and more complex in terms of verify that requirements are fulfilled at different design levels. This requires the simulation of the system and the checking of its timing and functional properties. model-driven design and UML give a reasonable solution to cope with such complexity since they have mechanisms to model and verify embedded systems. This paper presents a methodology which starts from UML/MARTE sequence diagrams with timing constraints and the automatic generation of executable SystemC/TLM and VHDL code with checkers from such diagrams. The simulation of the generated model allows to verify the specified sequence of exchanged information between components while checkers allow to verify that properties and timing constraints are met. Three case studies are used to show the validity of the approach and a less than linear increase of execution time overhead due to time observation and assertion checkers.

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Section: Hifmentioning

confidence: 99%

Section: Model and Constraint Specificationsmentioning

confidence: 99%

Section: Systemc/tlm Code Generation Of Wsn Application (Case Study #1)mentioning

confidence: 99%

Section: Figmentioning

confidence: 99%

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HDL code generation from UML/MARTE sequence diagrams for verification and synthesis

Ebeid

Fummi

Quaglia

2015

Des Autom Embed Syst

Self Cite

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“…Co-simulation would overcome this limitation [1], [16], but it would decrease simulation performance due to the frequent synchronization between different simulation environments. At the same time, many state-of-theart methodologies and tools allow to automatically convert HDLs to C++ and SystemC [3], [14], [22]. However, such tools focus on the reproduction of the IP functionality, with no concern for simulation performance and optimization.…”

Section: Introductionmentioning

confidence: 99%

Code Manipulation for Virtual Platform Integration

Vinco

Guarnieri

Fummi

2016

IEEE Trans. Comput.

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Simulation speed is crucial in virtual platforms, in order to enhance the design flow with early validation and design space exploration. This work tackles this challenge by focusing on two main techniques for speeding up virtual platform simulation, namely efficient data types implementation and a novel scheduling technique. Both the optimizations are obtained through code manipulation. The target language is C++ and its extensions (i.e., SystemC), that are the most widespread languages for virtual platform modeling and simulation. The optimization techniques are considered orthogonal, as they target different aspects of the simulated code. Experimental results prove the effectiveness of both the single techniques and of their combined application on complex case studies, with the result of reaching a maximum speedup of 70x in the simulation of a virtual platform.

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