Hierarchical Transactional Memory Protocol for Distributed Mixed-Criticality Embedded Systems

Owda, Zaher; Urbina, Moises; Obermaisser, Roman; Abuteir, Mohammed

doi:10.1109/dasc-picom-datacom-cyberscitec.2016.74

Cited by 3 publications

(1 citation statement)

References 30 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A good overview of transactional memories is given in [31]. In the context of mixed-critical real-time systems, HTM has been explored as hierarchical HTM on distributed embedded systems spanning over on-Chip and off-Chip networks [32].…”

Section: Related Workmentioning

confidence: 99%

Providing Integrity in Real-Time Networks-on-Chip

Rambo

Shang

Ernst

2019

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Mixed-critical real-time systems must meet strict integrity, resilience and timing constraints, as specified by safety standards. Due to the increasing threat of random hardware faults, efficiently achieving high reliability and dependability calls for cross-layer fault-tolerance solutions. This work introduces the Advanced Integrity Q-service (AIQ), a mechanism to ensure the integrity and predictability of on-Chip communication under random hardware faults. Devised for cross-layer and hierarchical fault-tolerance solutions, AIQ realizes low-overhead error detection in hardware and delegates error handling to arbitrary strategies in software. Experimental evaluation featuring benchmark applications and an industrial avionics use case shows that AIQ operates with high reliability and availability and low hardware and performance overheads. In a many-core mixed-critical platform under expected real-time scenarios, AIQ performs with execution time overhead between 1.4% and 7.1%.

show abstract

Section: Related Workmentioning

confidence: 99%