Hierarchical routing architectures in clustered 2D-mesh Networks-on-Chip

Winter, Markus; Prusseit, Steffen; Gerhard, P. Fettweis

doi:10.1109/socdc.2010.5682890

Cited by 35 publications

(20 citation statements)

References 6 publications

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“…Which has an impact on the EED and PLR. In fact, packet loss is mainly due to congestion in path, however, in case of link failure, packet can be loss due to time out [29,30].…”

Section: Rate Of Packet Lossmentioning

confidence: 99%

End to End QoS Metrics Modeling Based on Multi-application Environment in Network on Chip

Saadaoui¹,

Nasri²

2017

JCN

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To quantitatively measure quality of service (QoS) in Network on Chip (NoC), several related aspects of the network service are often considered, such as end to end delay (EED), Throughput (Thp), Packet loss rate (PLR), etc. However, until now, no standard method of performance measurement and fewer techniques have been used to provide its definition. In fact, few papers have developed different methods to modelize QoS in NoC and provided an efficient and flexible way to monitor QoS. The originality of our approach is based on a proposition of a QoSintellectual property module in NoC architecture to improve network performances. We implement an approach of QoS metrics modeling for NoC, using Analytic Hierarchy Process (AHP) on multi-parameter and multi-application for 4×4 mesh NoC environment. The results have shown that our QoS modeling approach is proven successful in providing a quantifiable representation. Therefore, QoS arbiter module interacts with other routers, the link utilization is balanced and network performance improved.

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“…Which has an impact on the EED and PLR. In fact, packet loss is mainly due to congestion in path, however, in case of link failure, packet can be loss due to time out [29,30].…”

Section: Rate Of Packet Lossmentioning

confidence: 99%

End to End QoS Metrics Modeling Based on Multi-application Environment in Network on Chip

Saadaoui¹,

Nasri²

2017

JCN

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“…The HNoC is a scalable solution [15]. It integrates low-diameter topologies, that aided by efficient flow control and routing mechanisms, minimizes the overall power consumption and NoC latency [16]. Our architecture integrates five key components: (1) low NoC/high NoC, (2) policy keeper, (3) configuration control, (4) security mechanisms, and (5) monitors.…”

Section: Our Approachmentioning

confidence: 99%

QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection

Sepúlveda

Pires

Gogniat

et al. 2012

International Journal of Reconfigurable Computing

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As electronic systems are pervading our lives, MPSoC (multiprocessor system-on-chip) security is becoming an important requirement. MPSoCs are able to support multiple applications on the same chip. The challenge is to provide MPSoC security that makes possible a trustworthy system that meets the performance and security requirements of all the applications. The network-on-chip (NoC) can be used to efficiently incorporate security. Our work proposes the implementation of QoSS (quality of security service) to overcome present MPSoC vulnerabilities. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. QoSS takes advantage of the NoC wide system visibility and critical role in enabling system operation, exploiting the NoC components to detect and prevent a wide range of attacks. In this paper, we present the implementation of a layered dynamic security NoC architecture that integrates agile and dynamic security firewalls in order to detect attacks based on different security rules. We evaluate the effectiveness of our approach over several MPSoCs scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of different security policies for several MPSoC applications.

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“…Therefore, we leave the issue of more advanced routing schemes to future work. The combination of XY routing and the previously describes addressing system of PyraMesh provides a deadlock free routing [12]. We illustrate the routing scheme in figure 9.…”

Section: Addressing and Routingmentioning

confidence: 99%

“…While the injection saturation rate of the concurrent topologies falls with the growth of the number of modules, the saturation rate of throughput optimized PyraMesh roughly remains constant and outperforms the SMesh by up-to 110.7% for a 128x128 system. We summarize latency reduction (in %) of latency optimized PyraMesh in [12] can be classified as a simple example of PyraMesh, in this paper we define a much broader variety of topologies and describe a methodology to suit the appropriate topologies to different sets of design goals. Moreover, the authors conclude in [12] that the addition of hierarchy levels on top of the base mesh is not area-cost effective -a conclusion that we refute throughout the paper.…”

Section: Performance Analysis and Simulationsmentioning

confidence: 99%

Handling global traffic in future CMP NoCs

Manevich

Cidon

Kolodny

2012

Proceedings of the International Workshop on System Level Interconnect Prediction

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It was recently shown that if computation locality is properly employed, Chip-Multi-Processors (CMP) traffic patterns can be modeled with a bandwidth version of Rent's rule. The Communication Probability Distributions (CPD) derived from the Rent's rule imply that most end to end packets are exchanged by nearest-neighbors.We show that, contrary to the common wisdom, while packets exchanged with nearest-neighbor dominate peer to peer traffic, their contribution to the overall NoC traffic decreases rapidly as the system grows. Correspondingly, the absolute bandwidth consumed by long distance packets (a.k.a. global packets) becomes dominant starting from medium-size systems, despite their low injection rate.To accommodate this phenomenon, we introduce PyraMesh -a novel family of multilevel hierarchical 2D mesh topologies resembling a pyramid structure. In PyraMesh, global packets are separated from the local ones and routed through the upper levels of the hierarchy. PyraMesh is shown to improve light-load latencies and raise the saturation point of the network to higher injection rates, as compared with previously presented NoC topologies.

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Hierarchical routing architectures in clustered 2D-mesh Networks-on-Chip

Cited by 35 publications

References 6 publications

End to End QoS Metrics Modeling Based on Multi-application Environment in Network on Chip

End to End QoS Metrics Modeling Based on Multi-application Environment in Network on Chip

QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection

Handling global traffic in future CMP NoCs

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