Hierarchical random simulation approach for the verification of S/390 CMOS multiprocessors

Abstract

In this paper an approach is presented for the hierarchical verification of the memory control units, I/O adapters and processor interconnect units as found in multiprocessor computer systems. It is shown how such units could be verified better and faster by the introduction of random executable timing diagrams and associated CAD tool support. Furthermore, it is shown how the timing diagrams for the unit network verification are easily derived from the timing diagrams specified for the units. The multiprocessor hardware test showed the effectiveness of the proposed verification approach.