2007
DOI: 10.1145/1217088.1217095
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Hierarchical partitioning of VLSI floorplans by staircases

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Cited by 2 publications
(16 citation statements)
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“…In this section, we briefly review monotone staircase channels and the birpartitioning framework in order to obtain them immediately after the floorplan stage. Methods for top-down hierarchical monotone staircase bipartitioning of VLSI floorplans, both in Area-balanced and Number-balanced bipartition appear in [5,7,9,12,13]. Area-balanced bipartition is employed when the area of the blocks in a given floorplan have significant variance, whereas Number-balanced bipartition is applicable for negligible variance in the area of the blocks.…”
Section: Preliminariesmentioning
confidence: 99%
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“…In this section, we briefly review monotone staircase channels and the birpartitioning framework in order to obtain them immediately after the floorplan stage. Methods for top-down hierarchical monotone staircase bipartitioning of VLSI floorplans, both in Area-balanced and Number-balanced bipartition appear in [5,7,9,12,13]. Area-balanced bipartition is employed when the area of the blocks in a given floorplan have significant variance, whereas Number-balanced bipartition is applicable for negligible variance in the area of the blocks.…”
Section: Preliminariesmentioning
confidence: 99%
“…Area-balanced bipartition is employed when the area of the blocks in a given floorplan have significant variance, whereas Number-balanced bipartition is applicable for negligible variance in the area of the blocks. In [12,13], the balanced bipartitioner used iterative max-flow based [23] min-cut algorithm and thereby incurred higher time complexity at each level of the hierarchy. In [5], emphasis has been given to the hierarchical number balanced monotone staircase bipartitioning using depth-first traversal method in linear time at a given level of the hierarchy.…”
Section: Preliminariesmentioning
confidence: 99%
“…Moreover, vias consume substantial routing area and pose as additional routing blockages in the routing regions impacting routability of the design. erefore, via minimization [31] 31], and (b) New [15] Recently, an early global routing (EGR) method STAIRoute [15] was proposed for early routability assessment of a floorplanned layout, facilitated by a monotone staircase cut based recursive floorplan bipartitioning framework [18,25,26]. ese bipartitioners work on any floorplan irrespective of their sliceability.…”
Section: Introductionmentioning
confidence: 99%
“…It also includes a recent floorplan based early global routability assessment tool STAIRoute [15].is work addresses an early version of unconstrained via minimization problem during early global routing by identifying a set of minimal bend routing regions in any floorplan, by a new recursive bipartitioning framework. ese regions facilitate monotone pa ern routing of a set of nets in the floorplan by STAIRoute.e area/number balanced floorplan bipartitionining is a multi-objective optimization problem and known to be NP-hard [25]. No existing approaches considered bend minimization as an objective and some of them incurred higher runtime overhead.…”
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confidence: 99%
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